Search results for "multivalued logic"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Dusan Guller	Procedural Semantics for Fuzzy Disjunctive Programs.	LPAR	2002	DBLP DOI BibTeX RDF	multivalued logic programming, logic in artificial intelligence, fuzzy logic, knowledge representation and reasoning, model theory, disjunctive logic programming
2	Mostafa H. Abd-El-Barr, M. N. Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
2	Susanto Rahardja, Bogdan J. Falkowski	Family of Fast Mixed Arithmetic Logic Transforms for Multiple-Valued Input Binary Functions. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	fast mixed arithmetic logic transforms, multiple-valued input binary functions, transform matrices, mixed arithmetic logic spectra, Boolean functions, transforms, matrix algebra, multivalued logic, multivalued logic circuits, inverse transforms
2	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
2	William A. Porter	Error Tolerant Design of Multivalued Logic Functions.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	polylogic, multivalued logic, switching functions, Error tolerance, statistical design
2	Kenneth C. Smith	The Prospects for Multivalued Logic: A Technology and Applications View.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	VLSI, fault detection, signal processing, multivalued logic, logic circuits, Arithmetic
2	Vason P. Srini	Iterative Realization of Multivalued Logic Systems.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	multivalued logic., + gate, U gates, general fault, fault detection, multiple faults, cellular array, Cell, gate
1	Asami Sasaki, Kujira Suzuki, Kin-ya Sugimoto, Hisashi Suzuki	New Boolean Multivalued Logic System Simplifying Inferences in Flexible Styles.	ICSEng	2011	DBLP DOI BibTeX RDF	logic, inference, flexible, Boolean, multivalued
1	Cristina Coppola, Giangiacomo Gerla, Annamaria Miranda	Point-free Foundation of Geometry and Multivalued Logic.	Notre Dame Journal of Formal Logic	2010	DBLP BibTeX RDF
1	Daniel Stamate	Queries with Multivalued Logic-Based Semantics for Imperfect Information Fusion.	ISMVL	2010	DBLP DOI BibTeX RDF	information fusion, multivalued logics, query equivalence, imperfect information, bilattices
1	M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli	Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Adam F. Gobi, Witold Pedrycz	Logic Minimization as an Efficient Means of Fuzzy Structure Discovery.	IEEE T. Fuzzy Systems	2008	DBLP DOI BibTeX RDF
1	Giangiacomo Gerla	Multivalued Logic to Transform Potential into Actual Objects.	Studia Logica	2007	DBLP DOI BibTeX RDF	Potential existence, point-free geometry, multi-valued logic, infinity
1	Zeljko Zilic, Katarzyna Radecka	Scaling and Better Approximating Quantum Fourier Transform by Higher Radices.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	quantum computing, Fourier transform, multivalued logic circuits, Walsh functions, multivariable systems
1	Silvia Ghilezan, Jovanka Pantovic, Jovisa D. Zunic	Separating Points by Parallel Hyperplanes - Characterization Problem.	IEEE Transactions on Neural Networks	2007	DBLP DOI BibTeX RDF
1	Marco Baioletti, Alfredo Milani, Valentina Poggioni, Silvia Suriani	A Multivalued Logic Model of Planning.	ECAI	2006	DBLP BibTeX RDF
1	Beata Konikowska, Wojciech Penczek	Model checking for multivalued logic of knowledge and time.	AAMAS	2006	DBLP DOI BibTeX RDF	multivalued modal logic, model checking, epistemic logic, interpreted systems
1	Bogdan J. Falkowski, Cheng Fu	Properties and relations of ternary linearly independent transforms [multivalued logic applications].	ISCAS	2005	DBLP DOI BibTeX RDF
1	Slim Abdennadher, Christophe Rigotti	Automatic generation of rule-based constraint solvers over finite domains.	ACM Trans. Comput. Log.	2004	DBLP DOI BibTeX RDF	Rule-based constraint programming, generation of solvers, finite domains
1	L. Gniewek, Jacek Kluska	Hardware implementation of fuzzy Petri net as a controller.	IEEE Transactions on Systems, Man, and Cybernetics, Part B	2004	DBLP DOI BibTeX RDF
1	T. Felicijan, Stephen B. Furber	An asynchronous ternary logic signaling system.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Witold Pedrycz, George Vukovich	An fMUX architecture: data modularization and mixed-mode system modeling.	Soft Comput.	2002	DBLP DOI BibTeX RDF	Fuzzy multiplexer, Mixed-mode modeling, OR and AND neurons, Learning, Multivalued logic, Digital systems, Logic modeling
1	Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal	Deriving Logic Systems for Path Delay Test Generation.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	simulation, timing analysis, Delay testing, multivalued logic, path delay faults, digital test
1	Mostafa H. Abd-El-Barr, M. N. Hasan, G. A. Hamid	On the Synthesis of MVL Functions Using Input and Output Phase Assignments. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	MVL functions synthesis, phase assignments, decomposition based mapping, input matrix, output matrix, matching-count matrix, output function number, maximum matching count, switching operations, switching operators, r-valued functions, logic synthesis, minimization, multivalued logic
1	Elena Dubrova, Jon C. Muzio, Bernhard von Stengel	Finding Composition Trees for Multiple-Valued Functions. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	composition trees, disjunctive decompositions, m-valued n-variable functions, test generation, multivalued logic, computation time, multiple-valued functions, recursive algorithm
1	Ewa Orlowska	Many-Valuedness and Uncertainty. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	modal information logics, many-valued modal logics, uncertain knowledge, calculus of information relations, Aristotelian syllogistic, multivalued logic
1	Boris A. Romov	Hyperclones on a Finite Set. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	hyperclones, composition-closed sets, multivalued operations, dual atomic, dual atoms, maximal hyperclones, multivalued logic, finite set
1	Noboru Takagi, Y. Nakamura, Kyoichi Nakashima	Set-Valued Functions and Regularity. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	set-valued functions, propositional connectives, n-variable ternary functions, /spl tau/-valued functions, regularity, multivalued logic, ternary logic
1	Zheng Tang, T. Yamaguchi, Koichi Tashima, Okihiko Ishizuka, Koichi Tanno	Multiple-Valued Immune Network Model and Its Simulations. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	multiple-valued immune network model, biological immune response network, B cells, T cells, experimentally testable predictions, letter recognition application, memory pattern, memory capacity, simulations, multivalued logic circuits, noise immunity
1	Alejandro F. González, Pinaki Mazumder	Compact Signed-Digit Adder Using Multiple-Valued Logic.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	O. D. Zhukov, Naphtali Rishe	Effective Computer Technology for Data Processing. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF
1	Zongmin Ma, Li Yan	Using multivalued logic in relational database containing null value.	J. Comput. Sci. Technol.	1996	DBLP DOI BibTeX RDF
1	Karl M. Fant, Scott A. Brandt	NULL Convention Logic/sup TM/: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis.	ASAP	1996	DBLP DOI BibTeX RDF	consistent logic, asynchronous digital circuit synthesis, symbolically complete logic, asynchronous digital circuits, asynchronous circuits, multivalued logic, three value logic, Boolean logic, NULL Convention Logic, four value logic
1	Stephen A. Fenner, Frederic Green, Steven Homer, Alan L. Selman, Thomas Thierauf, Heribert Vollmer	Complements of Multivalued Functions. (PDF / PS)	IEEE Conference on Computational Complexity	1996	DBLP DOI BibTeX RDF	multivalued functions, NPMV functions, coNPMV, complete functions, query hierarchy, functional analogue, Boolean hierarchy, computational complexity, complexity, multivalued logic, polynomial time hierarchy
1	Herman Akdag, Myriam Mokhtari	Approximative Conjunctions Processing by Multi-Valued Logic. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	conjunctions processing, neighbourhood degree, knowledge based systems, knowledge base, inference mechanisms, multivalued logic, production rule, multi-valued logic
1	Matthias Baaz, Christian G. Fermüller	Intuitionistic Counterparts of Finitely-Valued Logics. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	Kripke's model structures, finitely-valued logics, classical sequent calculus, cut-free complete, calculi, syntactical restriction, process algebra, multivalued logic, intuitionistic logic, Kripke structures
1	Jon T. Butler, J. L. Nowlin, Tsutomu Sasao	Planarity in ROMDD's of Multiple-Valued Symmetric Functions. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	ROMDD, multiple-valued symmetric function, reduced ordered multiple-valued decision diagram, logic values, voting functions, multivalued logic, decision diagrams, decision tables, multiple-valued functions, multiple-valued function
1	Rolf Drechsler	Verification of Multi-Valued Logic Networks. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued logic networks verification, ordered multi-valued decision diagrams, two-valued circuits, formal verification, heuristics, logic testing, directed graphs, directed acyclic graph, multivalued logic circuits, functional equivalence
1	Bogdan J. Falkowski, Susanto Rahardja	Complex Spectral Decision Diagrams. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	spectral decision diagrams, Complex Hadamard Transforms, multivalued logic, multiple-valued logic, decision diagrams, decision tables, multiple-valued functions, Hadamard transforms
1	Stefan Gerberding	DT - An Automated Theorem Prover for Multiple-Valued First-Order Predicate Logics. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	Deep Thought, multiple-valued first-order logics, lemma generation, tableau expansion, branch closure, theorem proving, multivalued logic, multiple-valued logics, quantifiers, first-order predicate logic, truth tables, automated theorem prover
1	Lucien Haddad, Jean Fugère	On the Lattice of Partial Clones on a Finite Set. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	partial clones, lattice, set theory, multivalued logic, finite set
1	Reiner Hähnle	Commodious Axiomatization of Quantifiers in Multiple-Valued Logic. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	commodious axiomatization, distribution quantifiers, lattice-based quantifiers, skolemized signed formulas, Boolean set lattices, Boolean functions, filters, multivalued logic, multiple-valued logic, quantifiers
1	S. Lehmke	Weight Structures for Approximate Reasoning with Weighted Expressions. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	weight structures, weighted expressions, fundamental relations model, semantic consequence, fuzzy logic, inference mechanisms, multivalued logic, many-valued logic, approximate reasoning, uncertainty handling
1	Lutz J. Micheel, Hans L. Hartnagel	Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion
1	Kyoichi Nakashima, Y. Nakamura, Noboru Takagi	Logic Expressions of Monotonic Multiple-Valued Functions. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	partial-ordering relation, unary operators, monotonic multiple-valued functions, monotonic p-valued functions, multivalued logic, multiple-valued logic, multiple-valued functions, logic functions
1	Antonio di Nola	Non-Archimedean Models of Lukasiewicz Logic. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	Lukasiewicz logic, nonarchimedean algebraic models, infinite-valued sentential calculus, Boolean functions, multivalued logic, Boolean algebra, MV-algebra
1	Come Rozon	On the Use of VHDL as a Multi-Valued Logic Simulator. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued logic simulator, ternary circuits, simulation, VHDL, logic CAD, functionality, circuit analysis computing, hardware description languages, digital circuits, multivalued logic circuits, timing specifications
1	Tsutomu Sasao, Jon T. Butler	A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	multiple-output switching functions, multi-terminal, multivalued logic, decision tables, computation time, switching functions, switching functions, multi-valued decision diagrams
1	Vlad P. Shmerko, Svetlana N. Yanushkevich, Vitaly G. Levashenko, I. Bondar	Technique of Computing Logic Derivatives for MVL-Functions. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	logic derivatives, partial direct, inverse derivatives, matrix approach, MVL switching circuit, truth vectors, multivalued logic, logic processing, MVL-functions
1	F. Sokhatsky	The Deepest Repetition-Free Decompositions of Non-Singular Functions of Finite-Valued Logics. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	nonsingular functions, finite-valued logics, repetition-free, isotopy change, commutation change, associative change, Boolean functions, Boolean functions, multivalued logic, three-valued logics
1	Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono	A Necessary and Sufficient Condition for Lukasiewicz Logic Functions. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	Lukasiewicz logic functions, Lukasiewicz multiple-valued logic, Lukasiewicz implication, logic design, multivalued logic, negation, multiple-valued functions, multiple-valued logic design
1	Hao Tang, Hung Chang Lin	Multi-Valued Decoder Based on Resonant Tunneling Diodes in Current Tapping Mode. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued decoder, current tapping mode, single peaked RTD sections, single literal function, simulation, decoding, circuit analysis computing, multivalued logic circuits, resonant tunnelling diodes, resonant tunneling diodes
1	Helmut Thiele	On Isomorphisms between the Lattice of Tolerance Relations and Lattices of Clusterings. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	lattice of tolerance relations, lattices of clusterings, one-to-one correspondences, classical set theory, bijections, complete atomistic boolean algebra, strongly model-compact coverings, cluster analysis, set theory, multivalued logic, equivalence classes, isomorphisms, similarity relations, mathematical foundations, lattice isomorphisms
1	Theo J. Powell	Consistently dominant fault model for tristate buffer nets.	VTS	1996	DBLP DOI BibTeX RDF	buffer circuits, consistently dominant fault model, tristate buffer nets, floating type faults, contention type faults, MISR signature loss, test pattern compression, VLSI, fault diagnosis, logic testing, integrated circuit testing, fault detection, fault location, integrated logic circuits, multivalued logic circuits, ternary logic, stuck faults
1	Valery A. Vardanian	On completely robust path delay fault testable realization of logic functions.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testable realization, two-level completely RPDFT realization, RPDFT-extension, input variables, VLSI, VLSI, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, integrated circuit testing, combinational circuits, combinational circuits, multivalued logic circuits, symmetric functions
1	Peter Wohl, John A. Waicukauski, Matthew Graf	Testing "untestable" faults in three-state circuits.	VTS	1996	DBLP DOI BibTeX RDF	three-state circuits, complex CMOS designs, nonconventional circuits, test generation techniques, circuit particularities, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, test coverage, multivalued logic circuits, computer testing, CPU time, test vector generation, untestable faults, automatic learning
1	Wenjun Wang, Claudio Moraga	Design of Multivalued Circuits using Genetic Algorithms. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF
1	Michel Billaud	Fatal Errors in Conditional Expressions (Extended Abstract).	ICALP	1996	DBLP DOI BibTeX RDF
1	Alessandro Saffiotti, Kurt Konolige, Enrique H. Ruspini	A Multivalued Logic Approach to Integrating Planning and Control.	Artif. Intell.	1995	DBLP DOI BibTeX RDF
1	Soumitra Bose, Vishwani D. Agrawal	Sequential logic path delay test generation by symbolic analysis.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
1	Mallika De, Bhabani P. Sinha	Testing of a parallel ternary multiplier using I/sup 2/L logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier
1	Eiji Harada, Janak H. Patel	Overhead reduction techniques for hierarchical fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multi-list-traversal method, one-pass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI
1	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	A cellular array designed from a Multiple-valued Decision Diagram and its fault tests.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple-valued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuck-at faults
1	Jacob Savir	Module level weighted random patterns.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
1	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
1	Wen Ching Wu, Chung-Len Lee, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
1	J. Beckman, T. C. Wesselkamper	The Radii of Sheffer Functions Over E(3). (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	Sheffer functions radii, two place function, least natural number, isotopy classes, E(3), symmetric Sheffer function, functions, multivalued logic
1	K. Wayne Current	Memory Circuits for Multiple-Valued Logic Voltage Signals. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	memory circuits, multiple valued logic voltage signals, voltage-mode CMOS multiple valued logic memory circuits, polysilicon-gate CMOS technology, SETUP clock mode, HOLD clock mode, multivalued logic circuits, integrated memory circuits, CMOS memory circuits
1	Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama	Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	quantum interference devices, MOS logic circuits, quantum device model, super pass gate, multiple-valued digital systems, VLSI devices, super pass transistor, multiple-valued VLSI systems, multiple-signal-level detection, multiple-valued universal logic module, multiple-valued image processing system, NMOS circuit, VLSI, multivalued logic circuits, semiconductor device models
1	Rolf Drechsler, Rolf Krieger, Bernd Becker	Random Pattern Fault Simulation in Multi-Valued Circuits. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	random pattern fault simulation, multi-valued circuits, multi-valued logic networks, fault diagnosis, logic testing, integrated circuit testing, fault simulator, circuit analysis computing, multivalued logic circuits, random pattern testability
1	Elena Dubrova, Dilian Gurov, Jon C. Muzio	The Evaluation of Full Sensitivity for Test Generation in MVL Circuits. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	full sensitivity evaluation, MVL circuits, functional level, m-valued n-variable functions, multi-valued logic circuits, fault diagnosis, logic testing, test generation, circuit analysis computing, multivalued logic circuits
1	Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama	Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic
1	Yutaka Hata, Naotake Kamiura, Kazuharu Yamato	On Input Permutation Technique for Multiple-Valued Logic Synthesis. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	input permutation technique, multiple-valued logic synthesis, multiple valued sum of products expressions, TSUM, minimal sum of products expressions, permuted logic values, randomly generated functions, input permutation, output permutation, minimization times, window literals, sum of products expressions, set literals, logic design, set theory, multivalued logic
1	Takahiro Hozumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Logic Design Using Multiple-Valued EXOR. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued EXOR, sum operation, multiple valued sum of products expression, binary EXOR of MINs expressions, three valued EXOR of MINs expression, three valued two variable functions, multiple valued EXOR of MINs expressions, MAX of MINs, TSUM of MINs expressions, logic design, neural nets, multivalued logic, logic minimization, minimisation of switching nets, neural computing, multiple valued logic design, multiple-valued logic design
1	A. K. Jain, Mostafa H. Abd-El-Barr, R. J. Bolton	Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function
1	Hiroaki Kikuchi, Noboru Takagi, Shohachiro Nakanishi, Masao Mukaidono	Uniqueness of Partially Specified Multiple-Valued Kleenean Function. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	partially specified multiple-valued Kleenean function, logic formula, logical connectives, identification problem, fuzzy logic, multivalued logic, uniqueness, necessary and sufficient condition
1	Tadeusz Luba	Decomposition of Multiple-Valued Functions. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	silicon space, PLA implementations, information storing systems, information systems, logic design, decomposition, logic synthesis, programmable logic arrays, multivalued logic, logic circuits, data bases, multiple-valued functions
1	Wendy MacCaull	Finite Algebraic Models for Residuated Logic. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	finite algebraic models, residuated logic, model pruning, nonclassical logics, combinatorial explosions, structure theorems, residuated algebras, theorem proving, inference mechanisms, search problems, multivalued logic, approximate reasoning, substructural logics, algebraic semantics, automated theorem prover
1	Keivan Navi, Daniel Etiemble	From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multivalued current mode CMOS circuits, voltage mode CMOS arithmetic operators, 3-valued current mode CMOS 2-input BSC adder, CMOS binary 4-2 counter, 1-digit Avizienis-like adder, adders, CMOS integrated circuits, integrated logic circuits, multivalued logic circuits, ternary logic, redundant number representation
1	Alioune Ngom, Corina Reischer, Ivan Stojmenovic	Classification of Functions and Enumeration of Bases of Set Logic under Boolean Compositions. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	set logic bases enumeration, functions classification, Boolean compositions, r-valued set logic, n-tuples, B-maximal sets, set logic, one-place example function, one-place set logic functions, B-Sheffer functions, Boolean functions, Boolean functions, set theory, multivalued logic
1	R. Oenning, Claudio Moraga	Properties of the Zhang-Watari Transform. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	2D multiple-valued Haar transform, 2D real valued Zhang-Watari transform, Haar spectrum, real arithmetic, permutation operation, extended 1D results, 2D Chrestenson transform, pattern partition, pattern recognition, patterns, transforms, multivalued logic, combinatorial mathematics
1	Grant Pogosyan, Akihiro Nozaki	Join-Irreducible Clones of Multiple-Valued Logic Algebra. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	join-irreducible clones, multiple valued logic algebra, synthetic means, lattice elements, join irreducible elements, unary functions, constructive criteria, graph theoretical property, one variable function, k valued logic, graph theory, set theory, multivalued logic, group theory, monoids, join operation, generating system
1	Boris A. Romov	Completeness Theory for Vector Partial Multiple-Valued Logic Functions. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	completeness theory, vector partial multiple-valued logic functions, completeness criterion, multiple-base invariant relations algebra, restricted quantifier free calculus, multivalued logic, Galois connection
1	M. Ryu, Michitaka Kameyama	Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	highly parallel multiple-valued linear digital system, k-ary operations, extended representation matrices, minimum critical path delay, unary operations, sparse representation matrices, output digit, decomposed unary operations, delays, multivalued logic circuits, sparseness, superposition, code assignment, signal representation
1	Tsutomu Sasao, Jon T. Butler	Planar Multiple-Valued Decision Diagrams. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	planar multiple-valued decision diagrams, monotone increasing functions, binary functions, field programmable gate arrays, programmable logic arrays, multivalued logic circuits, threshold logic, symmetric functions, threshold functions
1	Radomir S. Stankovic	Functional Decision Diagrams for Multiple-Valued Functions. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	functional decision diagrams, uniform interpretation, binary switching functions, MV functions, Reed-Muller-Fourier representations, Reed-Muller-Fourier coefficients, decision theory, multivalued logic, Galois fields, Galois field, switching functions, multiple valued functions, multiple-valued functions
1	Noboru Takagi, Hiroaki Kikuchi, Kyoichi Nakashima, Masao Mukaidono	A Characterization of Kleenean Functions. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	Kleenean functions, fuzzy logic functions, constants, indeterminate truth value condition handling, ambiguous states, fuzzy logic, functions, fuzzy set theory, multivalued logic
1	Zheng Tang, Okihiko Ishizuka, Koichi Tanno	Learning Multiple-Valued Logic Networks Based on Back Propagation. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued logic networks learning, canonical realization, initial parameters, neural nets, simulation results, backpropagation, backpropagation, multivalued logic, parameter space, functional completeness
1	Takao Waho	Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	resonant tunnelling transistors, resonant tunneling transistors, multiple-valued logic circuits, multiple stable states, coupled-quantum-well, monostable-multistable logic circuits, multivalued logic circuits, resonant tunneling diodes, circuit stability
1	Hui Min Wang, Chung-Len Lee, Jwu E. Chen	Factorization of Multi-Valued Logic Functions. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multi-valued logic function factorization, multi valued logic functions, rectangular covering problem, MVL algebraic factorization algorithm, MVL Boolean properties, purely algebraic factorization algorithm, multilevel implementation, Boolean method, MVL example functions, computational complexity, complexity, Boolean functions, multivalued logic
1	Shoujue Wang, Xunwei Wu, Hongjuan Feng	The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	high speed ternary logic gates, multiple /spl beta/ transistors, multiple emitter transistor, current gain, linear AND/OR gates, multi valued literal circuits, high speed multi valued logic circuits, multivalued logic circuits, logic gates, ternary logic, transistors
1	T. C. Wesselkamper, J. Danowitz	Some New Results for Multiple-Valued Genetic Algorithms. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued genetic algorithms, reproduction, classical multiple-valued logic, highly fit population members, genetic algorithms, convergence, selection, multivalued logic, mutation, convergence of numerical methods, genetic operators, theorems
1	Xunwei Wu, Xiexiong Chen, Jizhong Shen	Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	race-hazard, skip-hazard, multivalued combinational circuits, race hazards, AND/OR expression, skip hazard, multivalued circuits, fast transition, small load capacitor, combinational circuits, multivalued logic circuits, hazards and race conditions, input signals
1	Zeljko Zilic, Zvonko G. Vranesic	Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	Reed-Muller forms, sparse polynomial interpolation, MVL RM transforms, interpolation, multivalued logic, Reed-Muller codes, polynomial interpolation, incompletely specified functions, computationally efficient algorithm
1	Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli	A new switching-level approach to multiple-output functions synthesis.	VLSI Design	1995	DBLP DOI BibTeX RDF	switching-level, multiple-output functions synthesis, transistor level, randomly generated functions, logic CAD, timing constraints, circuit layout CAD, CMOS logic circuits, multivalued logic circuits, integrated circuit layout, minimisation of switching nets, area minimization, figures of merit
1	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
1	Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell	Statistical methods for delay fault coverage analysis.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities
1	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
1	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	VLSI Design	1995	DBLP DOI BibTeX RDF	stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
1	Alessandro Bogliolo, Maurizio Damiani	Synthesis of combinational circuits with special fault-handling capabilitie.	VTS	1995	DBLP DOI BibTeX RDF	combinational circuit synthesis, fault-handling capabilities, internal faults, multilevel logic optimization process, logic testing, redundancy, redundancy, design for testability, logic design, combinational circuits, logic CAD, multivalued logic, circuit optimisation, self-checking circuits, circuit reliability, fault-tolerant circuits