Search results for "nanometer design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen	Fast analog layout prototyping for nanometer design migration.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Scott Davidson	A second course on testing [review of System on Chip Test Architectures (Wang, L.-T et al., Eds.; 2007)].	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Omid Kavehie, Mostafa Rahimi Azghadi, Keivan Navi, Amir-Pasha Mirbaha	Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Dan Zhao, Yi Wang	MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Subhomoy Chattopadhyay	Low power design techniques for nanometer design processes: 65 nm and smaller.	SBCCI	2007	DBLP DOI BibTeX RDF	65 nm, low power, embedded design
1	Subhomoy Chattopadhyay, Rakesh Patel	Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Thomas W. Williams	EDA to the Rescue of the Silicon Roadmap.	ISQED	2007	DBLP DOI BibTeX RDF
1	Sanjay Gupta, Taranjit Kukal, Alok Tripathi, Raja Mitra, Ashish Patni, Siddarth Shetty	Tutorial T7B: RF Analysis and Simulation with Focus on RF SiP Methodology.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Rakesh Vattikonda, Wenping Wang, Yu Cao	Modeling and minimization of PMOS NBTI effect for robust nanometer design.	DAC	2006	DBLP DOI BibTeX RDF	reliability, variability, temperature, performance degradation, NBTI, threshold voltage
1	R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopal, N. Guruprasad, K. Subbarangaiah, Taher Abbasi, D. V. R. Murthy, P. Krishna Prasad, D. R. Gude	A Comprehensive SoC Design Methodology for Nanometer Design Challenges.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Uday Reddy Bandi, Murty Dasaka, Pavan K. Kumar	Design in reliability for communication designs.	DAC	2006	DBLP DOI BibTeX RDF	electro migration, nanometer design challenges, self heat, reliability, EDA tools
1	Samuel Rodríguez, Bruce L. Jacob	Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm).	ISLPED	2006	DBLP DOI BibTeX RDF	nanometer design, pipelined caches, cache design
1	Minsik Cho, David Z. Pan	BoxRouter: a new global router based on box expansion and progressive ILP.	DAC	2006	DBLP DOI BibTeX RDF	VLSI, congestion, global routing
1	Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt	On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST).	IOLTS	2005	DBLP DOI BibTeX RDF
1	Jasjeet Kaur	A Balanced Scorecard for Systemic Quality in Electronic Design Automation: An Implementation Method for an EDA Company.	ISQED	2005	DBLP DOI BibTeX RDF
1	Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar	The Certainty of Uncertainty: Randomness in Nanometer Design.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Janusz Rajski, Kan Thapar	Nanometer Design: What are the Requirements for Manufacturing Test?	DATE	2004	DBLP DOI BibTeX RDF
1	Greg Aldrich	100 DPPM in Nanometer Technology - Is it achievable?	ITC	2004	DBLP DOI BibTeX RDF
1	Jeong-Taek Kong	CAD for nanometer silicon design challenges and success.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1		Quality Challenges of the Nanometer Design Realm. (PDF / PS)	ISQED	2003	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf	Nanometer design: place your bets.	DAC	2003	DBLP DOI BibTeX RDF
1	Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind	Architecting ASIC libraries and flows in nanometer era.	DAC	2003	DBLP DOI BibTeX RDF	nanometer design, libraries, standard cell
1	Kyu-won Choi, Abhijit Chatterjee	UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI.	ISLPED	2003	DBLP DOI BibTeX RDF	device and interconnect co-optimization, nanometer design, time slack distribution, low-power design
1	Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi	Nanometer design: what hurts next...?	DAC	2002	DBLP DOI BibTeX RDF
1	Dennis Sylvester, Himanshu Kaul	Power-Driven Challenges in Nanometer Design.	IEEE Design & Test of Computers	2001	DBLP DOI BibTeX RDF
1	Dennis Sylvester, Himanshu Kaul	Future Performance Challenges in Nanometer Design.	DAC	2001	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang	Panel: Is Nanometer Design Under Control?	DAC	2001	DBLP DOI BibTeX RDF