Search results for "network synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Cliff C. N. Sze	ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.	ISPD	2010	DBLP DOI BibTeX RDF	VLSI, benchmarks, physical design, clock network synthesis
3	Cliff N. Sze, Phillip Restle, Gi-Joon Nam, Charles J. Alpert	Ispd2009 clock network synthesis contest.	ISPD	2009	DBLP DOI BibTeX RDF	benchmarks, physical design, vlsi, clock network synthesis
2	Kemal Sahin, Korhan Gürsoy, Amy Ciric	MINLP: Heat Exchanger Network Synthesis.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	HEN synthesis, Network synthesis, MINLP
2	Rui Zhang, Pallav Gupta, Niraj K. Jha	Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Kaijian Shi, Zhian Lin, Yi-Min Jiang	A Power Network Synthesis Method for Industrial Power Gating Designs.	ISQED	2007	DBLP DOI BibTeX RDF
2	Anand Rajaram, David Z. Pan	Variation tolerant buffered clock network synthesis with cross links.	ISPD	2006	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
2	Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha	Threshold network synthesis and optimization and its application to nanotechnologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Chieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee	Hierarchical power network synthesis for multiple power domain designs.	ISQED	2012	DBLP DOI BibTeX RDF
1	Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay	And-or-XOR Network Synthesis with Area-Power Trade-Off.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF
1	Jason Zheng Jiang, Malcolm C. Smith	Regular Positive-Real Functions and Five-Element Network Synthesis for Electrical and Mechanical Networks.	IEEE Trans. Automat. Contr.	2011	DBLP DOI BibTeX RDF
1	Sheng Chou, Cheng-Shen Han, Po-Kai Huang, Ko-Fan Tien, Tsung-Yi Ho	An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Tarun Mittal, Cheng-Kok Koh	Cross link insertion for improving tolerance to variations in clock network synthesis.	ISPD	2011	DBLP DOI BibTeX RDF
1	Beatriz A. Garro, Humberto Sossa, Roberto Antonio Vázquez	Artificial neural network synthesis by means of artificial bee colony (ABC) algorithm.	IEEE Congress on Evolutionary Computation	2011	DBLP DOI BibTeX RDF
1	Naotsuna Fujimori, Lu Liu, Shinji Hara, Daisuke Tsubakino	Hierarchical network synthesis for output consensus by eigenvector-based interlayer connections.	CDC-ECE	2011	DBLP DOI BibTeX RDF
1	Shreepad Panth, Sung Kyu Lim	Scan chain and power delivery network synthesis for pre-bond test of 3D ICs.	VTS	2011	DBLP DOI BibTeX RDF
1	Jianchao Lu, Yusuf Aksehir, Baris Taskin	Register On MEsh (ROME): A novel approach for clock mesh network synthesis.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Cliff C. N. Sze	The future of clock network synthesis.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Vijayalakshmi Srinivasan	Big Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Big chips, dark silicon, network scalability, thermal design power, large-scale designs, field-programmable gate arrays, hardware accelerators, dynamic voltage and frequency scaling, 3D integration, physical synthesis, clock network synthesis
1	István Heckl, Ferenc Friedler, L. T. Fan	Solution of separation-network synthesis problems by the P-graph methodology.	Computers & Chemical Engineering	2010	DBLP DOI BibTeX RDF
1	Timo Laukkanen, Tor-Martin Tveit, Vesa Ojalehto, Kaisa Miettinen, Carl-Johan Fogelholm	An interactive multi-objective approach to heat exchanger network synthesis.	Computers & Chemical Engineering	2010	DBLP DOI BibTeX RDF
1	R. Anantharaman, I. Nastad, B. Nygreen, T. Gundersen	The sequential framework for heat exchanger network synthesis - The minimum number of units sub-problem.	Computers & Chemical Engineering	2010	DBLP DOI BibTeX RDF
1	Anand Rajaram, David Z. Pan	MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham	Clock Network Synthesis with Concurrent Gate Insertion.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Miroslav Pajic, Shreyas Sundaram, Jerome Le Ny, George J. Pappas, Rahul Mangharam	The Wireless Control Network: Synthesis and robustness.	CDC	2010	DBLP DOI BibTeX RDF
1	Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young	A dual-MST approach for clock network synthesis.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Hendra Ishwara Nurdin, Matthew R. James, Andrew C. Doherty	Network Synthesis of Linear Dynamical Quantum Stochastic Systems.	SIAM J. Control and Optimization	2009	DBLP DOI BibTeX RDF
1	Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler	Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Josephine Antoniou, Ioannis Z. Koukoutsidis, Eva Jaho, Andreas Pitsillides, Ioannis Stavrakakis	Access network synthesis game in next generation networks.	Computer Networks	2009	DBLP DOI BibTeX RDF
1	Santosh N. Kabadi, R. Chandrasekaran, K. P. K. Nair	2-Commodity Integer Network Synthesis Problem.	Algorithmic Operations Research	2009	DBLP BibTeX RDF
1	Kemal Sahin, Korhan Gürsoy, Amy Ciric	Mixed Integer Linear Programming: Heat Exchanger Network Synthesis.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	HEN synthesis, Transshipment model, MILP
1	Hendra Ishwara Nurdin, Matthew R. James, Andrew C. Doherty	A network synthesis theorem for linear dynamical quantum stochastic systems.	CDC	2009	DBLP DOI BibTeX RDF
1	Yexin Zheng, Chao Huang	A novel Toffoli network synthesis algorithm for reversible logic.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan	Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs.	JCP	2008	DBLP DOI BibTeX RDF
1	Santosh N. Kabadi, J. Yan, Donglei Du, K. P. K. Nair	Integer Exact Network Synthesis Problem.	SIAM J. Discrete Math.	2008	DBLP DOI BibTeX RDF
1	Santosh N. Kabadi, Ramaswamy Chandrasekaran, K. P. K. Nair, Yash P. Aneja	Integer version of the multipath flow network synthesis problem.	Discrete Applied Mathematics	2008	DBLP DOI BibTeX RDF
1	David Ilsen, Ernst Josef Roebbers, Gert-Martin Greuel	Algebraic and Combinatorial Algorithms for Translinear Network Synthesis.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis	Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.	ISQED	2008	DBLP DOI BibTeX RDF	Transistor networks, logic synthesis, BDDs, Logical effort
1	Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
1	M. A. S. S. Ravagnani, J. A. Caballero	Optimal heat exchanger network synthesis with the detailed heat transfer equipment design.	Computers & Chemical Engineering	2007	DBLP DOI BibTeX RDF
1	Santosh N. Kabadi, Donglei Du	On-line Network Synthesis.	Algorithmic Operations Research	2007	DBLP BibTeX RDF
1	Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan	Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.	ISQED	2007	DBLP DOI BibTeX RDF
1	Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler	Exact sat-based toffoli network synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	synthesis, minimization, boolean satisfiability, reversible logic, quantum circuits
1	Robert Wille, Daniel Große	Fast exact Toffoli network synthesis of reversible logic.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Ivan Zelinka, Pavel Varacha	Synthesis of artificial neural networks by evolutionary methods.	DEXA Workshops	2007	DBLP DOI BibTeX RDF
1	Claudio Mattiussi, Dario Floreano	Analog Genetic Encoding for the Evolution of Circuits and Networks.	IEEE Trans. Evolutionary Computation	2007	DBLP DOI BibTeX RDF
1	Andrés F. Barbaro, Miguel J. Bagajewicz	Corrigendum to "New rigorous one-step MILP formulation for heat exchanger network synthesis" [Computers & Chemical Engineering 29 (2005) 1945-1976].	Computers & Chemical Engineering	2006	DBLP DOI BibTeX RDF
1	Min-Seok Kim, Jiang Hu	Associative skew clock routing for difficult instances.	DATE	2006	DBLP DOI BibTeX RDF
1	Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He	Wideband passive multiport model order reduction and realization of RLCM circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Andrés F. Barbaro, Miguel J. Bagajewicz	New rigorous one-step MILP formulation for heat exchanger network synthesis.	Computers & Chemical Engineering	2005	DBLP DOI BibTeX RDF
1	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Toffoli network synthesis with templates.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Krishnan Srinivasan, Karam S. Chatha	ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu	Minimizing peak current via opposite-phase clock tree.	DAC	2005	DBLP DOI BibTeX RDF	low power, physical design, clock network synthesis
1	Rogelio Palomera-Garcia	Generation of equivalent circuits by FTFN relocation.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan	Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
1	Rui Zhang, Pallav Gupta, Niraj K. Jha	Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Jiachuan Wang, Zhun Fan, Janis P. Terpenny, Erik D. Goodman	Knowledge interaction with genetic programming in mechatronic systems design using bond graphs.	IEEE Transactions on Systems, Man, and Cybernetics, Part C	2005	DBLP DOI BibTeX RDF
1	Jean François Maurras, Sonia Vanier	Network synthesis under survivability constraints.	4OR	2004	DBLP DOI BibTeX RDF	Survivable telecommunication networks, routing, complexity, multicommodity flows
1	B. Lin, D. C. Miller	Solving heat exchanger network synthesis problems with Tabu Search.	Computers & Chemical Engineering	2004	DBLP DOI BibTeX RDF
1	S. Kauchali, B. Hausberger, Diane Hildebrandt, David Glasser, Lorenz T. Biegler	Automating reactor network synthesis: finding a candidate attainable region for the water-gas shift (WGS) reaction.	Computers & Chemical Engineering	2004	DBLP DOI BibTeX RDF
1	Anand Rajaram, Jiang Hu, Rabi N. Mahapatra	Reducing clock skew variability via cross links.	DAC	2004	DBLP DOI BibTeX RDF	VLSI, physical design, variation, clock network synthesis
1	Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha	Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies.	DATE	2004	DBLP DOI BibTeX RDF
1	Kaj-Mikael Björk, Frank Pettersson	Optimization of Large-scale Heat Exchanger Network Synthesis Problems.	Modelling and Simulation	2003	DBLP BibTeX RDF
1	Michaela Plante, Brunilde Sansò	A Typology for Multi-Technology, Multi-Service Broadband Network Synthesis.	Telecommunication Systems	2002	DBLP DOI BibTeX RDF
1	Devert Wicker, Mateen M. Rizki, Louis A. Tamburino	E-Net: Evolutionary neural network synthesis.	Neurocomputing	2002	DBLP DOI BibTeX RDF
1	Marcus Randall, Elliot Tonkes	Solving Network Synthesis Problems Using Ant Colony Optimisation.	IEA/AIE	2001	DBLP DOI BibTeX RDF	heuristic search and telecommunications, autonomous agents, Ant colony optimisation
1	V. Cheushev, Svetlana N. Yanushkevich, Vlad P. Shmerko, Claudio Moraga, Joanna Kolodziejczyk	Information Theory Method for Flexible Network Synthesis.	ISMVL	2001	DBLP BibTeX RDF
1	Csanád Imreh	A New Well-Solvable Class of PNS Problems.	Computing	2001	DBLP DOI BibTeX RDF	AMS Subject Classifications: 90C27, 94C15
1	Balázs Imreh, J. Fülöp, Ferenc Friedler	A Note on the Equivalence of the Set Covering and Process Network Synthesis Problems.	Acta Cybern.	2000	DBLP BibTeX RDF
1	Vojislav Kecman	Comments on "discrete time neural network synthesis using input and output functions".	IEEE Transactions on Systems, Man, and Cybernetics, Part B	2000	DBLP DOI BibTeX RDF
1	Tadeusz Luba, Claudio Moraga, Svetlana N. Yanushkevich, M. Opoka, Vlad P. Shmerko	Evolutionary Multi-Level Network Synthesis in Given Design Style. (PDF / PS)	ISMVL	2000	DBLP DOI BibTeX RDF	information theory approach, genetic algorithms, parallel processing, circuit design
1	Sudipto Guha, Adam Meyerson, Kamesh Munagala	Hierarchical Placement and Network Design Problems.	FOCS	2000	DBLP DOI BibTeX RDF	subscriber loops, hierarchical placement, layered network design problems, constant approximations, bounded miss rates, minimum total cost, routing demand, layered caching scenarios, combinatorial approximation, multi-level facility location problem, load-balanced facility location problem, open facilities, access network design problem, resource allocation, facility location, cache storage, file organisation, approximation theory, hierarchical systems, network synthesis, hierarchical caching
1	David R. Karger, Maria Minkoff	Building Steiner Trees with Incomplete Global Knowledge.	FOCS	2000	DBLP DOI BibTeX RDF	combinational switching, incomplete global knowledge, network usage minimization, data item distribution, data-requesting clients, connection probability, fixed data path specification, concave cost functions, open facilities, minimum demand, bicriterion approximation, assignment cost, trees (mathematics), Steiner trees, client-server systems, facility location, minimisation, approximation theory, uncertainty handling, facility location problem, economies of scale, vertex, network synthesis, network design problems
1	Adam Meyerson, Kamesh Munagala, Serge A. Plotkin	Cost-Distance: Two Metric Network Design.	FOCS	2000	DBLP DOI BibTeX RDF	cost-distance problem, 2-metric network design, edge cost sum optimization, source-sink distance sum optimization, randomized approximation scheme, source number, logarithmic approximation, single-sink buy-at-bulk problem, variable pipe types, single-source multicast trees, delay properties, multi-level facility location, computational complexity, trees (mathematics), cost, Steiner tree, facility location, telecommunication network routing, edges, approximation theory, randomised algorithms, network synthesis
1	Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski	Retiming-based factorization for sequential logic optimization.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	finite stat machines, retiming, sequential synthesis
1	Vijay Lakamraju, Zahava Koren, C. Mani Krishna	Synthesis of Interconnection Networks: A Novel Approach.	DSN	2000	DBLP DOI BibTeX RDF	low diameter, fault tolerance, scalability, Interconnection networks, filtering, random regular graphs
1	Tadeusz Luba, Claudio Moraga, Svetlana N. Yanushkevich, Vlad P. Shmerko, Joanna Kolodziejczyk	Application of Design Style in Evolutionary Multi-Level Networks Synthesis.	EUROMICRO	2000	DBLP DOI BibTeX RDF	multi-level synthesis, information theory approach, parallelism, evolutionary design
1	Wolfram Schiffmann	Encoding feedforward networks for topology optimization by simulated evolution.	KES	2000	DBLP DOI BibTeX RDF
1	Cs. Holló, Z. Blázsik, Csanád Imreh, Z. Kovacs	On Merging Reduction of the Process Network Synthesis Problem.	Acta Cybern.	1999	DBLP BibTeX RDF
1	Ismet Bayraktaroglu, Arif Selçuk Ögrenci, Günhan Dündar, Sina Balkir, Ethem Alpaydin	ANNSyS: an Analog Neural Network Synthesis System.	Neural Networks	1999	DBLP DOI BibTeX RDF
1	Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya	An Integrated Approach for Synthesizing LUT Networks.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	Z. Blázsik, Cs. Holló, Balázs Imreh	On Decision-Mappings Related to Process Network Synthesis Problem.	Acta Cybern.	1998	DBLP BibTeX RDF
1	Xiaochao Sun, André Girard	A fast numerical algorithm for multi-rate network synthesis.	Telecommunication Systems	1998	DBLP DOI BibTeX RDF
1	Ferenc Friedler, L. T. Fan, Balázs Imreh	Process network synthesis: Problem definition.	Networks	1998	DBLP DOI BibTeX RDF
1	Chuanyi Ji, Demetri Psaltis	Network Synthesis through Data-Driven Growth and Decay.	Neural Networks	1997	DBLP DOI BibTeX RDF
1	Kalyan T. Talluri	Network synthesis with few edges.	Networks	1996	DBLP DOI BibTeX RDF
1	Branko Novakovic	Discrete time neural network synthesis using input and output activation functions.	IEEE Transactions on Systems, Man, and Cybernetics, Part B	1996	DBLP DOI BibTeX RDF
1	Roland W. Freund, Peter Feldmann	Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm.	ICCAD	1996	DBLP DOI BibTeX RDF	passive networks, Pade approximations, Lanczos algorithm, symmetric formulation, interconnect, network synthesis, reduced-order modeling
1	Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	A study of composition schemes for mixed apply/compose based construction of ROBDDs.	VLSI Design	1996	DBLP DOI BibTeX RDF	mixed apply/compose based construction, ROBDD, reduced ordered binary decision diagram, time-memory tradeoff, graph theory, composition, decomposition, heuristic algorithm, circuit CAD, circuit CAD, network synthesis, top down method, bottom up method
1	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Reed Muller form, AND-XOR network synthesis, fixed-polarity canonical expansion, genetic algorithm
1	José Luis Neves, Eby G. Friedman	Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF
1	Bernd Groß, Ulrich Hammel, Peter Maldaner, Andreas Meyer, Peter Roosen, Martin Schütz	Optimization of Heat Exchanger Networks by Means of Evolution Strategies.	PPSN	1996	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Synthesis of multiplier-less FIR filters with minimum number of additions.	ICCAD	1995	DBLP DOI BibTeX RDF	MCM based structures, iterative elimination, low pass FIR filters, circuit CAD, FIR filters, network synthesis, optimizing transformations, binary representations
1	Samit Chaudhuri, Stephen A. Blythe, Robert A. Walker	An exact methodology for scheduling in a 3D design space.	ISSS	1995	DBLP DOI BibTeX RDF	2D design space, 3D design space, 3D scheduling problem, Voyager design space exploration system, candidate clock lengths, clock length, globally optimal solution, schedule length, three dimensional scheduling, three-dimensional design space, two dimensional design space, scheduling, optimisation, high level synthesis, search problems, clocks, tight bounds, network synthesis, search space pruning
1	Enric Musoll, Jordi Cortadella	Scheduling and resource binding for low power.	ISSS	1995	DBLP DOI BibTeX RDF	data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding
1	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	ISSS	1995	DBLP DOI BibTeX RDF	DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules
1	Huy Nguyen, Abhijit Chatterjee	OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions.	ARVLSI	1995	DBLP DOI BibTeX RDF	linear network synthesis, OPTIMUS program, linear circuits, shift-and-add decomposition, behavioral synthesis tool, architectural transformations, numerical matrix transformation algorithms, number-splitting transformation, optimization, high level synthesis, multiplications, circuit CAD, circuit optimisation, matrix decomposition
1	R. Neil Braithwaite, Bir Bhanu	Error bound for multi-stage synthesis of narrow bandwidth Gabor filters. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	narrow bandwidth Gabor filters, multistage synthesis, weighted sum, spatially offset separable kernels, frequency offset, spatial subsampling rate, multistage filtering, general basis filter set design, error analysis, filtering theory, error bound, network synthesis
1	Hiroshi Sawada, Takayuki Suyama, Akira Nagoya	Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization.	ICCAD	1995	DBLP DOI BibTeX RDF	support minimization, Boolean resubstitution, functional decomposition, look-up table, ordered binary decision diagram
1	K. Vijayan Asari, C. Eswaran	An Optimization Technique for the Design of Multiple Valued PLA's.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple valued PLA design, output encoding, binary output, multiple function literal circuits, PLA size, encoding, minimization, programmable logic arrays, adders, adder, many-valued logics, minimisation, multiple valued logic, logic arrays, optimization technique, network synthesis
1	David S. Feldman	Fuzzy Network Synthesis with Genetic Algorithms.	ICGA	1993	DBLP BibTeX RDF