Search results for "network-on-chip"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Jason Cong, Chunyue Liu, Glenn Reinman	ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip.	DAC	2010	DBLP DOI BibTeX RDF	application-specific Network-on-Chip, deadlock-free routing
3	Cristinel Ababei	Network on chip design and optimization using specialized influence models.	DAC	2010	DBLP DOI BibTeX RDF	VFI design style, optimization, network on chip, influence model
3	Björn Osterloh, Harald Michalik, Björn Fiethe	SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs.	ARCS	2009	DBLP DOI BibTeX RDF	SoCWire, dynamic reconfigurable system, Sytem-on-Chip, Network-on-Chip, SRAM-based FPGA, VMC
3	Dietmar Tutsch, Miroslaw Malek	Comparison of network-on-chip topologies for multicore systems considering multicast and local traffic.	SimuTools	2009	DBLP DOI BibTeX RDF	simulation, performance, multicast, network-on-chip, multicore processor
3	Hamid Hajabdolali Bazzaz, Marjan Sirjani, Ramtin Khosravi, Shamim Taheri	Modeling networking issues of network-on-chip: a coloured petri nets approach.	SimuTools	2009	DBLP DOI BibTeX RDF	modeling, network-on-chip, coloured petri nets
3	Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam	Multiband RF-interconnect for reconfigurable network-on-chip communications.	SLIP	2009	DBLP DOI BibTeX RDF	fdma, morfic, rf-interconnect, network-on-chip, reconfigurable, chip multiprocessor
3	Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam	A DP-network for optimal dynamic routing in network-on-chip.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	optimal and sub-optimal routing, dynamic programming, network-on-chip, adaptive routing
3	Suboh A. Suboh, Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazawi	An interconnection architecture for network-on-chip systems.	Telecommunication Systems	2008	DBLP DOI BibTeX RDF	Switching and routing, Network on chip, Network analysis, Modeling and simulation, On-chip interconnects
3	Hsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee	Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures.	DELTA	2008	DBLP DOI BibTeX RDF	network-on-chip architectures, scheduling, mapping, circuit-switched networks
3	Claudia Rusu, Cristian Grecu, Lorena Anghel	Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems.	DELTA	2008	DBLP DOI BibTeX RDF	fault tolerance, network-on-chip, checkpoint, recovery, rollback, message log, failure rate, traffic load
3	Nader Bagherzadeh, Masaru Matsuura	Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip.	ITNG	2008	DBLP DOI BibTeX RDF	System-on-Chip, Network-on Chip, communication protocol
3	Fahimeh Jafari, Mohammad Hossien Yaghmaee, Mohammad Sadegh Talebi, Ahmad Khonsari	Max-Min-Fair Best Effort Flow Control in Network-on-Chip Architectures.	ICCS	2008	DBLP DOI BibTeX RDF	Network-on-Chip, flow control, Max-Min fairness
3	Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner	Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture.	NOCS	2008	DBLP DOI BibTeX RDF	DSPIN, ANOC, physical implementation, FAUST, bi-synchronous FIFO, network-on-chip, NoC
3	Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang	Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF	interconnnection, reliability, low power, network-on-chip
3	Mikkel Bystrup Stensgaard, Jens Sparsø	ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology.	NOCS	2008	DBLP DOI BibTeX RDF	Communication, System-on-Chip, Network-on-Chip, Reconfigurable, Application-specific
3	Santanu Kundu, Santanu Chattopadhyay	Mesh-of-tree deterministic routing for network-on-chip architecture.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	deterministic routing., mesh-of-tree (mot), interconnection networks, system-on-chip (soc), network-on-chip (noc)
3	Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri	Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture.	ANCS	2007	DBLP DOI BibTeX RDF	network-on-chip, low-power design
3	Lei Zhang 0008, Huawei Li, Xiaowei Li	A Routing Algorithm for Random Error Tolerance in Network-on-Chip.	HCI	2007	DBLP DOI BibTeX RDF	fault tolerance, routing, reliability, Network-on-Chip, error detecting, error correcting
3	Baojun Qiao, Feng Shi, Weixing Ji	THIN: A New Hierarchical Interconnection Network-on-Chip for SOC.	ICA3PP	2007	DBLP DOI BibTeX RDF	multicast, System-on-Chip, Network-on-Chip, network topology
3	Tobias Bjerregaard, Shankar Mahadevan	A survey of research and practices of Network-on-chip.	ACM Comput. Surv.	2006	DBLP DOI BibTeX RDF	Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions
3	Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota	Evaluation of SEU and crosstalk effects in network-on-chip switches.	SBCCI	2006	DBLP DOI BibTeX RDF	network-on-chip, crosstalk, single-event upset
3	Mário P. Véstias, Horácio C. Neto	Area and performance optimization of a generic network-on-chip architecture.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGA, system-on-chip, network-on-chip
3	Lap-Fai Leung, Chi-Ying Tsui	Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems.	DAC	2006	DBLP DOI BibTeX RDF	routing, network-on-chip, latency
3	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	BIST for Network-on-Chip Interconnect Infrastructures.	VTS	2006	DBLP DOI BibTeX RDF	interconnect infrastructure, unicast test, multicast test, built-in self-test, network-on-chip
3	Seung Eun Lee, Nader Bagherzadeh	Increasing the throughput of an adaptive router in network-on-chip (NoC).	CODES+ISSS	2006	DBLP DOI BibTeX RDF	adaptive router, interconnection network, chip-multiprocessor, wormhole routing, network-on-chip (NoC)
3	Prabhat Avasare, Vincent Nollet, Jean-Yves Mignolet, Diederik Verkest, Henk Corporaal	Centralized end-to-end flow control in a best-effort network-on-chip.	EMSOFT	2005	DBLP DOI BibTeX RDF	run-time communication management, network-on-chip
3	Krishnan Srinivasan, Karam S. Chatha	A technique for low energy mapping and routing in network-on-chip architectures.	ISLPED	2005	DBLP DOI BibTeX RDF	core mapping, routing, network-on-chip, automated design, mesh topology
3	Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini	Fault tolerance overhead in network-on-chip flow control schemes.	SBCCI	2005	DBLP DOI BibTeX RDF	fault tolerance, network on chip, error correction, flow control
3	Daniel Wiklund, Dake Liu	Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip.	IWSOC	2005	DBLP DOI BibTeX RDF	basestation, scheduling, Network on chip, 3G, WCDMA
3	Yang Yu, Mei Yang, Yulu Yang, Yingtao Jiang	A RDT-Based Interconnection Network for Scalable Network-on-Chip Designs.	ITCC	2005	DBLP DOI BibTeX RDF	routing, scalability, interconnection network, Network-on-Chip, torus
3	Andreas Hansson, Kees Goossens, Andrei Radulescu	A unified approach to constrained mapping and routing on network-on-chip architectures.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	quality-of-service, routing, system-on-chip, mapping, network-on-chip
3	Andrea Bona, Vittorio Zaccaria, Roberto Zafalon	Low Effort, High Accuracy Network-on-Chip Power Macro Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF	Network-on-Chip power analysis, communication based low power design, system-level energy optimization
3	Rodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo	When reconfigurable architecture meets network-on-chip.	SBCCI	2004	DBLP DOI BibTeX RDF	multiprocessor, system on chip, network on chip, reconfigurable architecture
3	Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde	Operating-system controlled network on chip.	DAC	2004	DBLP DOI BibTeX RDF	operating system, network on chip, MP-SoC
3	Jian Liu, Meigen Shen, Li-Rong Zheng, Hannu Tenhunen	System level interconnect design for network-on-chip using interconnect IPs.	SLIP	2003	DBLP DOI BibTeX RDF	interconnect IP, network on chip, interconnect, bandwidth optimization
3	Heiko Zimmer, Axel Jantsch	A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	fault tolerance, network-on-chip, bus encoding
2	Amlan Ganguly, Kevin Chang, Sujay Deb, Partha Pratim Pande, Benjamin Belzer, Christof Teuscher	Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	on-chip antenna, wireless communication, Network-on-chip, multicore, small-world network
2	Fucen Zeng, Lin Qiao, Wei Wang	PEPCP: A Power-Efficient Parallel Coherence Protocol for Large-Scale Network-on-Chip.	ICPP	2011	DBLP DOI BibTeX RDF	Network on chip, chip multiprocessors, cache coherence protocol
2	Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Ananth Kalyanaraman	Network-on-Chip Hardware Accelerators for Biological Sequence Alignment.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	DNA/protein sequence alignment, on-chip parallelism, bioinformatics, Network-on-chip, hardware acceleration
2	Alexandre Guerre, Nicolas Ventroux, Raphaël David, Alain Mérigot	Hierarchical Network-on-Chip for Embedded Many-Core Architectures.	NOCS	2010	DBLP DOI BibTeX RDF	hierarchical network on chip, area efficiency
2	Dmitri Vainbrand, Ran Ginosar	Network-on-Chip Architectures for Neural Networks.	NOCS	2010	DBLP DOI BibTeX RDF	Neural Network, Network-on-Chip
2	Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra	Low power nanoscale buffer management for network on chip routers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nanoscale technology noc, soc, noc, router, dynamic power management
2	Chi-Fu Chang, Yarsun Hsu	A System Exploration Platform for Network-on-Chip.	ISPA	2010	DBLP DOI BibTeX RDF	NoC simulator, Application-driven design, Network on chip, Simulation framework
2	Kees Goossens, Andreas Hansson	The aethereal network on chip after ten years: goals, evolution, lessons, and future.	DAC	2010	DBLP DOI BibTeX RDF	network on chip, rate control, circuit switching
2	Yiyuan Xie, Mahdi Nikdast, Jiang Xu, Wei Zhang 0012, Qi Li, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Weichen Liu	Crosstalk noise and bit error rate analysis for optical network-on-chip.	DAC	2010	DBLP DOI BibTeX RDF	optical network-on-chip, crosstalk, BER, SNR
2	Wei Hu, Binbin Wu, Bin Xie, Tianzhou Chen, Lianghua Miao	A Bypass Optimization Method for Network on Chip.	CIT	2010	DBLP DOI BibTeX RDF	network on chip, router, bypass
2	Wei Hu, Jianliang Ma, Binbin Wu, Lihan Ju, Tianzhou Chen	Distributed On-Chip Operating System for Network on Chip.	CIT	2010	DBLP DOI BibTeX RDF	distributed system, operating system, network on chip
2	Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh	Area and Power-efficient Innovative Network-on-Chip Architecurte.	PDP	2010	DBLP DOI BibTeX RDF	interconnection network, system-on-chip (SoC), power-efficient, power-optimization, Network-on-Chip (NoC), area-efficient
2	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan	Compiler directed network-on-chip reliability enhancement for chip multiprocessors.	LCTES	2010	DBLP DOI BibTeX RDF	reliability, compiler, noc, chip multiprocessors
2	Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King, Shau-Yin Tseng	NTPT: on the end-to-end traffic prediction in the on-chip networks.	DAC	2010	DBLP DOI BibTeX RDF	end-to-end traffic prediction, network-on-chip, many-core
2	Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li	Cost-driven 3D integration with interconnect layers.	DAC	2010	DBLP DOI BibTeX RDF	interconnect service layer, three-dimensional integrated circuit, network-on-chip
2	Mike Brugge, Mohammed A. S. Khalid	Design and evaluation of a parameterizable NoC router for FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, architecture, system-on-chip, network-on-chip, design space exploration, router
2	Vincenzo Rana, Donatella Sciuto	A novel design framework for the design of reconfigurable systems based on NoCs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	network-on-chip, reconfigurable computing, design flow, mapping algorithm
2	Pavel Ghosh, Arunabha Sen	Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints.	SAC	2010	DBLP DOI BibTeX RDF	greedy randomized heuristic, multi-processor system-on-chip (MPSoC), integer linear program, network-on-chip (NoC), voltage islanding
2	Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest	Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC)
2	Daniel U. Becker, William J. Dally	Allocator implementations for network-on-chip routers.	SC	2009	DBLP DOI BibTeX RDF
2	Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh	Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip.	ITNG	2009	DBLP DOI BibTeX RDF	parallel and pipeline processing, security, network-on-chip, block cipher, software implementation
2	Ling Wang, Jianwen Zhang, Xiaoqing Yang, Dongxin Wen	Router with centralized buffer for network-on-chip.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	centralized buffer, architecture, router, NoC
2	Muhammad Aqeel Wahlah, Kees G. W. Goossens	Modeling reconfiguration in a FPGA with a hardwired network on chip.	IPDPS	2009	DBLP DOI BibTeX RDF
2	Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, Janet Meiling Wang	Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Jian Wang, Yubai Li, Qicong Peng, Taiqiu Tan	A dynamic priority arbiter for Network-on-Chip.	SIES	2009	DBLP DOI BibTeX RDF
2	Mahmoud Moadeli, Partha P. Maji, Wim Vanderbauwhede	Quarc: A High-Efficiency Network on-Chip Architecture.	AINA	2009	DBLP DOI BibTeX RDF	Quarc, Network On Chip, ASIC
2	Gul N. Khan, Victor Dumitriu	Throughput-based network-on-chip topology generation and analysis.	CCECE	2009	DBLP DOI BibTeX RDF
2	Minghua Tang, Xiaola Lin	An Advanced NoP Selection Strategy for Odd-Even Routing Algorithm in Network-on-Chip.	ICA3PP	2009	DBLP DOI BibTeX RDF	OE routing algorithm, SoC, Network-on-Chip, adaptive routing, selection strategy
2	Paul Bogdan, Radu Marculescu	Statistical physics approaches for network-on-chip traffic characterization.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	fractional calculus, systems-on-chip, networks-on-chip, multi-processor systems, master equation
2	Matthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø	Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	routing, system-on-chip, mapping, network-on-chip, synthesis, configuration
2	David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester	Vicis: a reliable network for unreliable silicon.	DAC	2009	DBLP DOI BibTeX RDF	hard faults, fault tolerance, built-in-self-test, Network-on-Chip, reconfiguration, torus, N-modular redundancy
2	Xinyu Li, Omar Hammami	Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, multiprocessor, network on chip
2	Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz	Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.	SBCCI	2009	DBLP DOI BibTeX RDF	reconfigurable router, fault tolerance, reliability, network-on-chip, NoC
2	Dan Zhao, Yi Wang	SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod	Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Paul Beekhuizen, Dee Denteneer, Ivo J. B. F. Adan	Analysis of a tandem network model of a single-router Network-on-Chip.	Annals OR	2008	DBLP DOI BibTeX RDF
2	Praveen Bhojwani, Rabi N. Mahapatra	Robust Concurrent Online Testing of Network-on-Chip-Based SoCs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Zhonghai Lu, Axel Jantsch	TDM Virtual-Circuit Configuration for Network-on-Chip.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Graham Schelle, Dirk Grunwald	Exploring FPGA network on chip implementations across various application and network loads.	FPL	2008	DBLP DOI BibTeX RDF
2	Byung-Gyu Ahn, Jun-Mo Jung, Jong-Wha Chong	Power-Aware Test Framework for Network-on-Chip.	ICONS	2008	DBLP DOI BibTeX RDF	test, low-power, NoC
2	Thomas Lenart, Henrik Svensson, Viktor Öwall	A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing.	DELTA	2008	DBLP DOI BibTeX RDF	SCENIC, Network-on-Chip, Reconfigurable Computing, TLM, 2D Mesh
2	Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston	A Lightweight Fault-Tolerant Mechanism for Network-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF	fault tolerance, reliability, Network-on-Chip, routing algorithm, deadlock avoidance, on-chip network
2	Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach	A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.	NOCS	2008	DBLP DOI BibTeX RDF	NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous
2	Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khonsari, Mohammad Hossien Yaghmaee	Proportionally-fair best effort flow control in network-on-chip architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Flexible parallel pipeline network-on-chip based on dynamic packet identity management.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Michael Hübner, Lars Braun, Diana Göhringer, Jürgen Becker	Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Zhen Zhang, Alain Greiner, Sami Taktak	A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip.	DAC	2008	DBLP DOI BibTeX RDF	2D-Mesh NoC, DSPIN, MP2-SoC, fault-tolerant, reconfiguration, routing algorithm
2	Shan Yan, Bill Lin	Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Jari Nurmi, Manfred Glesner, Fernando Moraes	Validation of executable application models mapped onto network-on-chip platforms.	SIES	2008	DBLP DOI BibTeX RDF
2	Christian Paukovits, Hermann Kopetz	Concepts of Switching in the Time-Triggered Network-on-Chip.	RTCSA	2008	DBLP DOI BibTeX RDF
2	Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Tang	Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor.	DATE	2008	DBLP DOI BibTeX RDF
2	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Multicast Parallel Pipeline Router Architecture for Network-on-Chip.	DATE	2008	DBLP DOI BibTeX RDF
2	Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina	xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures.	PDP	2008	DBLP DOI BibTeX RDF	NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques
2	Fahimeh Jafari, Mohammad Sadegh Talebi, Ahmad Khonsari, Mohammad Hossien Yaghmaee	A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization.	ISPAN	2008	DBLP DOI BibTeX RDF	Congestion control, Network-on-Chip, iterative algorithm
2	Xiao Canwen, Zhang Minxuan, Dou Yong, Zhao Zhitong	Dimensional Bubble Flow Control and Fully Adaptive Routing in the 2-D Mesh Network on Chip.	EUC	2008	DBLP DOI BibTeX RDF
2	Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi	MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC.	DDECS	2008	DBLP DOI BibTeX RDF
2	Alexander D. Rast, Shufan Yang, Muhammad Mukaram Khan, Stephen B. Furber	Virtual synaptic interconnect using an asynchronous network-on-chip.	IJCNN	2008	DBLP DOI BibTeX RDF
2	M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam	CMP network-on-chip overlaid with multi-band RF-interconnect.	HPCA	2008	DBLP DOI BibTeX RDF
2	Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das	Performance and power optimization through data compression in Network-on-Chip architectures.	HPCA	2008	DBLP DOI BibTeX RDF
2	Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel	ROAdNoC: runtime observability for an adaptive network on chip architecture.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini	A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Chen-Ling Chou, Radu Marculescu	Contention-aware application mapping for Network-on-Chip communication architectures.	ICCD	2008	DBLP DOI BibTeX RDF
2	Huaxi Gu, Jiang Xu, Zheng Wang	ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	microresonator, low power, network on chip, optical interconnect, router architecture, loss
2	Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. Kandemir	Application mapping for chip multiprocessors.	DAC	2008	DBLP DOI BibTeX RDF	NoC (Network on Chip), compilers, power optimization, chip multiprocessing, application mapping