Search results for "networks-on-chip"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam	Trace-driven optimization of networks-on-chip configurations.	DAC	2010	DBLP DOI BibTeX RDF	networks-on-chip, virtual channel, greedy heuristics
3	ShouYi Yin, LeiBo Liu, ShaoJun Wei	Buffer planning for application-specific networks-on-chip design.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	buffer planning, optimization, design automation, networks-on-chip (NoC)
3	Leonel Tedesco, Fabien Clermidy, Fernando Moraes	A path-load based adaptive routing algorithm for networks-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	quality of service, networks on chip, dynamic routing, traffic monitoring
3	Duo Ding, David Z. Pan	OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture.	SLIP	2009	DBLP DOI BibTeX RDF	photonic networks-on-chip, low power, computer aided design, high performance
3	Wooyoung Jang, David Z. Pan	An SDRAM-aware router for Networks-on-Chip.	DAC	2009	DBLP DOI BibTeX RDF	Networks-on-Chip, memory, flow control, router
3	Ümit Y. Ogras, Radu Marculescu	Analysis and optimization of prediction-based flow control in networks-on-chip.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	congestion control, networks-on-chip, flow control, Multi-processor systems
3	Ümit Y. Ogras, Radu Marculescu, Diana Marculescu	Variation-adaptive feedback control for networks-on-chip with multiple clock domains.	DAC	2008	DBLP DOI BibTeX RDF	dynamic voltage-frequency scaling, voltage-frequency island, networks-on-chip, MPSoC, feedback control, parameter variation
3	Ahmed A. Morgan, Haytham Elmiligi, M. Watheq El-Kharashi, Fayez Gebali	Application-specific networks-on-chip topology customization using network partitioning.	IFMT	2008	DBLP DOI BibTeX RDF	application-specific networks-on-chip (ASNoC), core graph, optimization, analysis, topology, network partitioning
3	Piotr Dziurzanski, Tomasz Maka	Stream Transfer Balancing Scheme Utilizing Multi-Path Routing in Networks on Chip.	ARC	2008	DBLP DOI BibTeX RDF	stream-based processing, tapeworm routing, Ford-Fulkerson method, Networks on Chip, wormhole routing
3	Balasubramanian Sethuraman, Ranga Vemuri	Multicasting based topology generation and core mapping for a power efficient networks-on-chip.	ISLPED	2007	DBLP DOI BibTeX RDF	packet reduction, power-efficient core mapping, multicast, networks-on-chip, mesh topology
3	Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar	A design methodology for application-specific networks-on-chip.	ACM Trans. Embedded Comput. Syst.	2006	DBLP DOI BibTeX RDF	regular topology, architecture, methodology, networks-on-chip, Application-specific
3	Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, Jef L. van Meerbergen	An event-based monitoring service for networks on chip.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	monitoring, debugging, Networks-on-Chip
3	Balasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri	LiPaR: A light-weight parallel router for FPGA-based networks-on-chip.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	SoCRouter, FPGA, networks-on-chip
3	Cesar Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin	ParIS: a parameterizable interconnect switch for networks-on-chip.	SBCCI	2004	DBLP DOI BibTeX RDF	FPGA, systems-on-chip, networks-on-chip
2	Qiaoyan Yu, Meilin Zhang, Paul Ampadu	A comprehensive Networks-on-Chip simulator for error control explorations.	NOCS	2011	DBLP BibTeX RDF
2	Radu David, Paul Bogdan, Radu Marculescu, Ümit Y. Ogras	Dynamic power management of voltage-frequency island partitioned Networks-on-Chip using Intel's Single-chip Cloud Computer.	NOCS	2011	DBLP BibTeX RDF
2	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.	NOCS	2011	DBLP BibTeX RDF
2	Cristinel Ababei, Hamed Sajjadi Kia, Om Prakash Yadav, Jingcao Hu	Energy and reliability oriented mapping for regular Networks-on-Chip.	NOCS	2011	DBLP BibTeX RDF
2	Arpit Joshi, Madhu Mutyam	Prevention flow-control for low latency torus networks-on-chip.	NOCS	2011	DBLP BibTeX RDF
2	Qiaoyan Yu, Paul Ampadu	Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip.	NOCS	2010	DBLP DOI BibTeX RDF	permanent error, splitting transmission, spare wire, reliability, Network-on-chip, transient error
2	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs)
2	Ali Ahmadinia, Alireza Shahrabi	Adaptive Router Architecture for Optimising Quality of Service in Networks-on-Chip.	CIT	2010	DBLP DOI BibTeX RDF	Networks-on-Chip
2	Young Hoon Kang, Taek-Jun Kwon, Jeffrey T. Draper	Fault-Tolerant Flow Control in On-chip Networks.	NOCS	2010	DBLP DOI BibTeX RDF	fault-tolerant router, soft-error handling, networks-on-chip
2	Yvain Thonnart, Romain Lemaire, Fabien Clermidy	Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms.	NOCS	2010	DBLP DOI BibTeX RDF	Distributed Systems, Networks-on-Chip
2	Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesus Camacho, Federico Silla, José Duato	Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing.	NOCS	2010	DBLP DOI BibTeX RDF	Fault-tolerance, Routing, Networks-on-chip
2	Paul Bogdan, Miray Kas, Radu Marculescu, Onur Mutlu	QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors.	NOCS	2010	DBLP DOI BibTeX RDF	Self-Similar Stochastic Processes, Multi-fractal Analysis, Networks-on-Chip, Chip Multi-Processors
2	Luciano Ost, Guilherme Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp, Fernando Moraes	A high abstraction, high accuracy power estimation model for networks-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	high abstraction modeling, networks-on-chip, power modeling
2	Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi, Luca Benini	Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	link design techniques, network-on-chip
2	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
2	Marcelo Daniel Berejuck, Cesar Albenes Zeferino	Adding mechanisms for QoS to a network-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	FPGA, systems-on-chip, networks-on-chip
2	Sami Taktak, Jean Lou Desbarbieux, Emmanuelle Encrenaz	A tool for automatic detection of deadlock in wormhole networks on chip.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	interconnection networks, networks on chip, Deadlock, wormhole routing
2	Anthony Leroy, Dragomir Milojevic, Diederik Verkest, Frédéric Robert, Francky Catthoor	Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti	Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Performance evaluation, Routing protocols, Interconnection architectures
2	Érika F. Cota, Fernanda Gusmão de Lima Kastensmidt, Maico Cassel, Marcos Herve, Pedro Almeida, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski	A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Assaf Shacham, Keren Bergman, Luca P. Carloni	Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner	PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels.	PATMOS	2008	DBLP DOI BibTeX RDF
2	Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi	A simplified executable model to evaluate latency and throughput of networks-on-chip.	SBCCI	2008	DBLP DOI BibTeX RDF	performance evaluation, modeling, networks-on-chip
2	Bart Vermeulen, Kees Goossens, Siddharth Umrani	Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip.	NOCS	2008	DBLP DOI BibTeX RDF	communication-centric debug, debug, network-on-chip, design for debug
2	Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah	Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects.	NOCS	2008	DBLP DOI BibTeX RDF
2	Chen-Ling Chou, Radu Marculescu	User-Aware Dynamic Task Allocation in Networks-on-Chip.	DATE	2008	DBLP DOI BibTeX RDF
2	Paul Gratz, Boris Grot, Stephen W. Keckler	Regional congestion awareness for load balance in networks-on-chip.	HPCA	2008	DBLP DOI BibTeX RDF
2	Shan Yan, Bill Lin	Design of application-specific 3D Networks-on-Chip architectures.	ICCD	2008	DBLP DOI BibTeX RDF
2	Nicola Concer, Michele Petracca, Luca P. Carloni	Distributed flit-buffer flow control for networks-on-chip.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	latency-insensitive protocols, network-on-chip
2	Tushar Krishna, Amit Kumar 0002, Patrick Chiang, Mattan Erez, Li-Shiuan Peh	NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Hybrid interconnects, Networks-on-chip, Packet-switching
2	Vaclav Dvorak	Communication Performance of Mesh- and Ring-Based NoCs.	ICN	2008	DBLP DOI BibTeX RDF	Tera-scale platform, Networks on chip, collective communications
2	Francisco Gilabert Villamón, Simone Medardoni, Davide Bertozzi, Luca Benini, María Engracia Gómez, Pedro López, José Duato	Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.	NOCS	2008	DBLP DOI BibTeX RDF	Interconnection networks, networks on chip, topologies, chip design
2	Francesca Palumbo, Simone Secchi, Danilo Pani, Luigi Raffo	A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs.	SAMOS	2008	DBLP DOI BibTeX RDF	Dual-mode switching, Non-exclusive switching, Networks on Chip, Circuit switching
2	Federico Angiolini, Paolo Meloni, Salvatore Carta, Luigi Raffo, Luca Benini	A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Vasilis F. Pavlidis, Eby G. Friedman	3-D Topologies for Networks-on-Chip.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Brett Feero, Partha Pratim Pande	Performance Evaluation for Three-Dimensional Networks-On-Chip.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Everton Carara, Aline Mello, Fernando Moraes	Communication Models in Networks-on-Chip.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
2	Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu	Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency.	SiPS	2007	DBLP DOI BibTeX RDF
2	Assaf Shacham, Keren Bergman, Luca P. Carloni	The Case for Low-Power Photonic Networks on Chip.	DAC	2007	DBLP DOI BibTeX RDF
2	Lap-Fai Leung, Chi-Ying Tsui	Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands.	DAC	2007	DBLP DOI BibTeX RDF
2	Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes	DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.	VTS	2007	DBLP DOI BibTeX RDF
2	Andreas Hansson, Martijn Coenen, Kees Goossens	Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip.	DATE	2007	DBLP DOI BibTeX RDF
2	Ümit Y. Ogras, Radu Marculescu	Analytical router modeling for networks-on-chip performance analysis.	DATE	2007	DBLP DOI BibTeX RDF
2	Jan Willem van den Brand, Calin Ciordas, Kees Goossens, Twan Basten	Congestion-controlled best-effort communication for networks-on-chip.	DATE	2007	DBLP DOI BibTeX RDF
2	Andreas Hansson, Martijn Coenen, Kees Goossens	Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	quality-of-service, system-on-chip, network-on-chip, time-division-multiplexing
2	Edgard de Faria Corrêa, Leonardo Alves de Paula e Silva, Flávio Rech Wagner, Luigi Carro	Fitting the router characteristics in NoCs to meet QoS requirements.	SBCCI	2007	DBLP DOI BibTeX RDF	QoS, embedded systems, real time, systems-on-chip, networks-on-chip
2	Leonel Tedesco, Fernando Moraes, Ney Calazans	Buffer sizing for QoS flows in wormhole packet switching NoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	quality of service, networks on chip, traffic modeling, buffer sizing
2	Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu	Towards Open Network-on-Chip Benchmarks.	NOCS	2007	DBLP DOI BibTeX RDF	performance evaluation, metrics, benchmarks, networks-on-chip
2	Jingcao Hu, Ümit Y. Ogras, Radu Marculescu	System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Balasubramanian Sethuraman, Ranga Vemuri	Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip.	FPL	2006	DBLP DOI BibTeX RDF
2	Balasubramanian Sethuraman	Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip.	FPL	2006	DBLP DOI BibTeX RDF
2	José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes	Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	Yuan-Long Jeang, Chung-Wei Hung, Chuen-Muh Chiang	A Methodology Based on Maximal-Profit Spanning Tree for Designing Application Specific Networks on Chip (ASNOC).	ICICIC	2006	DBLP DOI BibTeX RDF
2	José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis	Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Axel Jantsch	Models of Computation for Networks on Chip.	ACSD	2006	DBLP DOI BibTeX RDF
2	Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli	A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip.	DAC	2006	DBLP DOI BibTeX RDF	re-order buffers, fault-tolerance, routing, systems on chip, networks on chip, flow control, multi-path
2	Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach	A DFT Architecture for Asynchronous Networks-on-Chip.	European Test Symposium	2006	DBLP DOI BibTeX RDF
2	Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli	A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	systems-on-chip, networks-on-chip, buffers, area
2	Ümit Y. Ogras, Radu Marculescu	Prediction-based flow control for network-on-chip traffic.	DAC	2006	DBLP DOI BibTeX RDF	congestion control, networks-on-chip, flow control, multi-processor systems
2	Sergio Tota, Mario R. Casu, Luca Macchiarulo	Implementation analysis of NoC: a MPSoC trace-driven approach.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	networks on chip, wormhole routing, multiprocessor systems-on-chip, deflection routing
2	Fabio Wronski, Eduardo Wenzel Brião, Flávio Rech Wagner	Evaluating Energy-Aware Task Allocation Strategies for MPSOCS.	DIPES	2006	DBLP DOI BibTeX RDF	Simulation, Networks-on-Chip, Task Allocation, Multiprocessor SoCs, Energy Estimation
2	Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes	Virtual channels in networks on chip: implementation and evaluation on hermes NoC.	SBCCI	2005	DBLP DOI BibTeX RDF	performance, network-on-chip, virtual channel
2	Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar	An Asynchronous Router for Multiple Service Levels Networks on Chip.	ASYNC	2005	DBLP DOI BibTeX RDF
2	Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans	MAIA: a framework for networks on chip generation and verification.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Daewook Kim, Manho Kim, Gerald E. Sobelman	FPGA-Based CDMA Switch for Networks-on-Chip.	FCCM	2005	DBLP DOI BibTeX RDF
2	Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar	H.264 HDTV Decoder Using Application-Specific Networks-On-Chip.	ICME	2005	DBLP DOI BibTeX RDF
2	Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli	Self-calibrating networks-on-chip.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Kwanho Kim, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo	An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Stefano Santi, Bill Lin, Ljupco Kocarev, Gian Mario Maggio, Riccardo Rovatti, Gianluca Setti	On the impact of traffic statistics on quality of service for networks on chip.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar	A methodology for design, modeling, and analysis of networks-on-chip.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng	Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz.	ICCD	2005	DBLP DOI BibTeX RDF
2	Ümit Y. Ogras, Jingcao Hu, Radu Marculescu	Key research problems in NoC design: a holistic perspective.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	Networks-on-Chip motivation, problem formulation, proposed solutions and open research problems, systems-on-chip, multi-processor systems
2	Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das	A low latency router supporting adaptivity for on-chip interconnects.	DAC	2005	DBLP DOI BibTeX RDF	networks, networks-on-chip, interconnection, adaptive routing
2	Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Flávio Rech Wagner, Altamiro Amadeu Susin	Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures.	SBCCI	2005	DBLP DOI BibTeX RDF	mapping and optimization algorithms, systems-on-chip, networks-on-chip
2	José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin	Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation.	SBCCI	2005	DBLP DOI BibTeX RDF	traffic effect, networks-on-chip, energy estimation, application mapping
2	Tapani Ahonen, David A. Sigüenza-Tortosa, Hong Bin, Jari Nurmi	Topology optimization for application-specific networks-on-chip.	SLIP	2004	DBLP DOI BibTeX RDF	application-specific network, platform design, network-on-chip, topology optimization
2	Jingcao Hu, Radu Marculescu	DyAD: smart routing for networks-on-chip.	DAC	2004	DBLP DOI BibTeX RDF	systems-on-chip, networks-on-chip, router design
2	Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli	×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip.	DATE	2004	DBLP DOI BibTeX RDF	Systems on Chips, Networks on Chips, SystemC, application-specific, latency-insensitive design
2	Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees G. W. Goossens, Om Prakash Gangwal	Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach.	DATE	2004	DBLP DOI BibTeX RDF
2	Jingcao Hu, Radu Marculescu	Application-specific buffer space allocation for networks-on-chip router design.	ICCAD	2004	DBLP DOI BibTeX RDF
2	Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin	Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture.	ICCD	2004	DBLP DOI BibTeX RDF
2	Srinivasan Murali, Giovanni De Micheli	SUNMAP: a tool for automatic topology selection and generation for NoCs.	DAC	2004	DBLP DOI BibTeX RDF	systems on chip, mapping, networks on chip, topology, SystemC
2	Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, E. Waterlander	Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.	DATE	2003	DBLP DOI BibTeX RDF
1	Nitin, Durg Singh Chauhan	Stochastic communication for application-specific Networks-on-Chip.	The Journal of Supercomputing	2012	DBLP DOI BibTeX RDF
1	Nishit Ashok Kapadia, Sudeep Pasricha	A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands.	Integration	2012	DBLP DOI BibTeX RDF
1	Xinyu Wang, Zhigang Yu, Huazhen Xu	A Simple and Efficient Input Selection Function for Networks-on-Chip.	ICDCN	2012	DBLP DOI BibTeX RDF