Search results for "on-chip communication"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi	System-level PVT variation-aware power exploration of on-chip communication architectures.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	PVT variation, on-chip communication architectures, performance exploration, high-level synthesis, power estimation, digital systems
3	Xinping Zhu, Sharad Malik	A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	on-chip communication architecture, network-on-chip, multiprocessor system, object-oriented modeling, packet-switching network, design exploration, bus, Retargetable simulation
3	Sujan Pandey, Manfred Glesner, Max Mühlhäuser	Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture.	SBCCI	2005	DBLP DOI BibTeX RDF	on-chip communication architecture synthesis, optimization, algorithms
2	Stamatis G. Kavadias, Manolis Katevenis, Michail Zampetakis, Dimitrios S. Nikolopoulos	On-chip communication and synchronization mechanisms with cache-integrated network interfaces.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	explicit communication, inter-processor synchronization, cache, network interface
2	Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi	Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Mohammad Abdullah Al Faruque, Jörg Henkel	QoS-supported On-chip Communication for Multi-processors.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	quality of services, Networks on chips, arbitration, multi-processor, service class
2	Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Mohammad Abdullah Al Faruque, Rudolf Krist, Jörg Henkel	ADAM: run-time agent-based distributed application mapping for on-chip communication.	DAC	2008	DBLP DOI BibTeX RDF	agent-based application mapping, on-chip communication
2	Like Yan, Qingsong Shi, Tianzhou Chen, Guobing Chen	An On-chip Communication Mechanism Design in the Embedded Heterogeneous Multi-core Architecture.	ICNSC	2008	DBLP DOI BibTeX RDF
2	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt	Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Mohammad Abdullah Al Faruque, Jörg Henkel	Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures.	DATE	2008	DBLP DOI BibTeX RDF
2	Woo-Cheol Kwon, Sung-Min Hong, Sungjoo Yoo, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo	An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication.	DATE	2008	DBLP DOI BibTeX RDF
2	Maurice Sebastian, Rolf Ernst	Modelling and designing reliable on-chip-communication devices in MPSoCs with real-time requirements.	ETFA	2008	DBLP DOI BibTeX RDF
2	Hyung Gyu Lee, Naehyuck Chang, Ümit Y. Ogras, Radu Marculescu	On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	MPEG-2 encoder, system-on-chip, Networks-on-chip, FPGA prototype, point-to-point
2	Nan Wang, Azeez Sanusi, Peiyi Zhao, Shaheen Mohamed, Magdy A. Bayoumi	PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design.	SiPS	2007	DBLP DOI BibTeX RDF
2	Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley	Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus.	ASYNC	2007	DBLP DOI BibTeX RDF
2	Tianzhou Chen, Guobing Chen, Hongjun Dai, Qingsong Shi	A function-based on-chip communication design in the heterogeneous multi-core architecture.	MUE	2007	DBLP DOI BibTeX RDF
2	Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel	Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding.	DATE	2007	DBLP DOI BibTeX RDF
2	Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel	Run-time adaptive on-chip communication scheme.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi	Communication Architecture Synthesis of Cascaded Bus Matrix.	ASP-DAC	2007	DBLP DOI BibTeX RDF	AMBA3 AXI, cascaded bus matrix, on-chip communication architecture, bus topology, encoding method, traffic group encoding, simulated annealing, design space exploration
2	Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana	The LOTTERYBUS on-chip communication architecture.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk	On-Chip Communication in Run-Time Assembled Reconfigurable Systems.	ICSAMOS	2006	DBLP DOI BibTeX RDF
2	Praveen Bhojwani, Rabi N. Mahapatra	Core Network Interface Architecture and Latency Constrained On-Chip Communication.	ISQED	2006	DBLP DOI BibTeX RDF
2	Sujan Pandey, Manfred Glesner	Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture.	FPL	2006	DBLP DOI BibTeX RDF
2	Guang Liang, Axel Jantsch	Adaptive Power Management for the On-Chip Communication Network.	DSD	2006	DBLP DOI BibTeX RDF
2	Sujan Pandey, Nurten Utlu, Manfred Glesner	Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Sujan Pandey, Tudor Murgan, Manfred Glesner	Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Yawen Niu, Jinian Bian, Haili Wang, Kun Tong	An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design.	CSCWD (Selected Papers)	2006	DBLP DOI BibTeX RDF
2	Sujan Pandey, Manfred Glesner	Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.	DAC	2006	DBLP DOI BibTeX RDF	communication bus synthesis, voltage scaling
2	Sujan Pandey, Manfred Glesner	Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Marcello Coppola	Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network.	IOLTS	2006	DBLP DOI BibTeX RDF
2	Mohammad Abdullah Al Faruque, Gereon Weiss, Jörg Henkel	Bounded arbitration algorithm for QoS-supported on-chip communication.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	bounded arbitration algorithm, quality of services, networks-on-chips
2	Juha Plosila, Pasi Liljeberg, Jouni Isoaho	Modelling and Refinement of an On-Chip Communication Architecture.	ICFEM	2005	DBLP DOI BibTeX RDF
2	Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey	FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology.	DAC	2005	DBLP DOI BibTeX RDF	communication architectures, on-chip bus
2	Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias	A distributed FIFO scheme for on chip communication.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Design space exploration for optimizing on-chip communication architectures.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	Jian Liang, Andrew Laffely, S. Srinivasan, Russell Tessier	An architecture and compiler for scalable on-chip communication.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Kanishka Lahiri, Anand Raghunathan	Power analysis of system-level on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	system-on-chip, network-on-chip, low-power design, power analysis, communication architectures
2	Xinping Zhu, Wei Qin, Sharad Malik	Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	on-chip communication architecture, simulator synthesis, multiprocessor system, packet-switching network, design exploration, bus, retargetable simulation
2	Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek	Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures.	FPL	2003	DBLP DOI BibTeX RDF
2	Vijay Raghunathan, Mani B. Srivastava, Rajesh K. Gupta	A survey of techniques for energy efficient on-chip communication.	DAC	2003	DBLP DOI BibTeX RDF	low power design, power management, communication architectures, system-on-chip design, energy efficient design
2	Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh	Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.	DATE	2003	DBLP DOI BibTeX RDF
2	Robert Siegmund, Dietmar Müller	Efficient modeling and synthesis of on-chip communication protocols for network-on-chip design.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli	On-chip communication design: roadblocks and avenues.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	GALS, on-chip networks, latency-insensitive design
2	Xinping Zhu, Sharad Malik	A hierarchical modeling framework for on-chip communication architectures.	ICCAD	2002	DBLP DOI BibTeX RDF
2	Ilkka Saastamoinen, David A. Sigüenza-Tortosa, Jari Nurmi	Interconnect IP Node for Future System-on-Chip Designs.	DELTA	2002	DBLP DOI BibTeX RDF	System-on-Chip, reuse, on-chip communication, packet network
2	Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani	A Network on Chip Architecture and Design Methodology.	ISVLSI	2002	DBLP DOI BibTeX RDF	System on Chip, IP, Platform based design, On-chip communication
2	Kanishka Lahiri, Sujit Dey, Anand Raghunathan	Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures.	VLSI Design	2001	DBLP DOI BibTeX RDF
2	Kees G. W. Goossens	A protocol and memory manager for on-chip communication.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Rishad A. Shafik, Bashir M. Al-Hashimi	Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Reza Nourmandi-Pour, Nafiseh Mousavian, Ahmad Khadem-Zadeh	BIST for network on chip communication infrastructure based on combination of extended IEEE 1149.1 and IEEE 1500 standards.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Zheng Li, Moustafa Mohamed, Xi Chen, Hongyu Zhou, Alan Rolf Mickelson, Li Shang, Manish Vachharajani	Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication.	JETC	2011	DBLP DOI BibTeX RDF
1	Giacomo Paci, Davide Bertozzi, Luca Benini	Variability compensation for full-swing against low-swing on-chip communication.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Ling Wang, Chunda Ding, Shenghai Zhong, Jianwen Zhang	GNLS: a hybrid on-chip communication architecture for SoC designs.	IJHPSA	2011	DBLP DOI BibTeX RDF
1	Dan Zhao, Yi Wang, Jian Li, Takamaro Kikkawa	Design of multi-channel wireless NoC to improve on-chip communication capacity!	NOCS	2011	DBLP BibTeX RDF
1	Jo C. Ebergen, Bill Coates, Austin Lee	Long-Distance On-chip Communication Using GasP.	ASYNC	2011	DBLP DOI BibTeX RDF
1	Masahiro Fujita	Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols.	ATVA	2011	DBLP DOI BibTeX RDF
1	Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini	ReliNoC: A reliable network for priority-based on-chip communication.	DATE	2011	DBLP DOI BibTeX RDF
1	Bharath Phanibhushana, Kunal P. Ganeshpure, Sandip Kundu	Task model for on-chip communication infrastructure design for multicore systems.	ICCD	2011	DBLP DOI BibTeX RDF
1	Faiz-ul Hassan, Wim Vanderbauwhede, Fernando Rodríguez Salazar	Performance Analysis of On-Chip Communication Structures under Device Variability.	IJERTCS	2010	DBLP DOI BibTeX RDF
1	Zheng Shi, Alan Burns, Leandro Soares Indrusiak	Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching.	IJERTCS	2010	DBLP DOI BibTeX RDF
1	Naoya Onizawa, Takahiro Hanyu	Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Balal Ahmad, Ali Ahmadinia, Tughrul Arslan	High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media.	Journal of Systems Architecture - Embedded Systems Design	2010	DBLP DOI BibTeX RDF
1	Zheng Shi, Alan Burns	Schedulability analysis and task mapping for real-time on-chip communication.	Real-Time Systems	2010	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Nan Wang, Azeez Sanusi, Peiyi Zhao, Mohamed A. Elgamel, Magdy A. Bayoumi	PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design.	Signal Processing Systems	2010	DBLP BibTeX RDF
1	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho	Process variation tolerant on-chip communication using receiver and driver reconfiguration.	ISQED	2010	DBLP DOI BibTeX RDF
1	Ulhas Deshmukh, Vineet Sahula	Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Marie Rouvière, Emmanuelle Bourdel, Sébastien Quintanel, Bertrand Granado	VHDL-AMS model of RF-Interconnect System for Global On-Chip Communication.	FDL	2010	DBLP BibTeX RDF
1	Dan Liu 0003, Yi Feng, Jingjin Zhou, Dong Tong, Xu Cheng, Keyi Wang	TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures.	SoCC	2010	DBLP DOI BibTeX RDF
1	Thomas Ebi, Mohammad Abdullah Al Faruque, Jörg Henkel	NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architecture.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Wooyoung Jang, David Z. Pan	Application-aware NoC design for efficient SDRAM access.	DAC	2010	DBLP DOI BibTeX RDF	QoS, memory, flow control, router, NoC, on-chip communication
1	Man Cao, Bin Xin, Fuming Qiao, Qingsong Shi, Tianzhou Chen, Like Yan	Distributed Memory Management Units Architecture for NoC-based CMPs.	CIT	2010	DBLP DOI BibTeX RDF	memory management unit, network on chip, on-chip communication
1	Bruce Mathewson	The evolution of SOC interconnect and how NOC fits within it.	DAC	2010	DBLP DOI BibTeX RDF	AMBA AXI, network on chip
1	Donglai Dai, Aniruddha Vaidya, Roy Saharoy, Seungjoon Park, Dongkook Park, Hariharan L. Thantry, Ralf Plate, Elmar Maas, Akhilesh Kumar, Mani Azimi	FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, routing algorithm, on-chip interconnect, router architecture
1	Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra	Low power nanoscale buffer management for network on chip routers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nanoscale technology noc, soc, noc, router, dynamic power management
1	Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun	Power-efficient variation-aware photonic on-chip network management.	ISLPED	2010	DBLP DOI BibTeX RDF	networks on chip, optical interconnects, nanophotonics
1	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan	Compiler directed network-on-chip reliability enhancement for chip multiprocessors.	LCTES	2010	DBLP DOI BibTeX RDF	reliability, compiler, noc, chip multiprocessors
1	Mohammad Abdullah al Faruque	Runtime Adaptive System-on-Chip Communication Architecture.		2009	RDF
1	Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran	Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	converter synthesis, protocol compatibility, System-on-chip, automatic design
1	Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta	Low-Power, High-Speed Transceivers for Network-on-Chip Communication.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen	Scalability of network-on-chip communication architecture for 3-D meshes.	NOCS	2009	DBLP DOI BibTeX RDF
1	Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol	Performance and power efficient on-chip communication using adaptive virtual point-to-point connections.	NOCS	2009	DBLP DOI BibTeX RDF
1	Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanovic, Vladimir Stojanovic	Silicon-photonic clos networks for global on-chip communication.	NOCS	2009	DBLP DOI BibTeX RDF
1	Ling Wang, Feng Wu, Jianwen Zhang, Yingtao Jiang	Reconfigurable Global Network Local Bus (RGNLS): A Hybrid On-Chip Communication Architecture for Area-Efficient, Dynamically Reconfigurable SoC Designs.	ESA	2009	DBLP BibTeX RDF
1	Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe Sun	Latency criticality aware on-chip communication.	DATE	2009	DBLP BibTeX RDF
1	Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair C. Bruce, Pieter van der Wolf, Tomas Henriksson	Flow regulation for on-chip communication.	DATE	2009	DBLP BibTeX RDF
1	Giacomo Paci, Davide Bertozzi, Luca Benini	Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels.	DATE	2009	DBLP BibTeX RDF
1	Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel	Configurable links for runtime adaptive on-chip communication.	DATE	2009	DBLP BibTeX RDF
1	Young-Pyo Joo, Sungchan Kim, Soonhoi Ha	On-chip communication architecture exploration for processor-pool-based MPSoC.	DATE	2009	DBLP BibTeX RDF
1	Zhonghai Lu, Dimitris Brachos, Axel Jantsch	A flow regulator for On-Chip Communication.	SoCC	2009	DBLP DOI BibTeX RDF
1	Chenjie Yu, Xiangrong Zhou, Peter Petrov	Low-power inter-core communication through cache partitioning in embedded multiprocessors.	SBCCI	2009	DBLP DOI BibTeX RDF	low-power cache architectures, low-power cache coherence, MPSoC, on-chip communication
1	Glenn Leary, Karam S. Chatha	Automated technique for design of NoC with minimal communication latency.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	best-effort communication, network-on-chip, synthesis, latency
1	Shidhartha Das, David Blaauw, David M. Bull, Krisztián Flautner, Rob Aitken	Addressing design margins through error-tolerant circuits.	DAC	2009	DBLP DOI BibTeX RDF
1	Sudeep Pasricha	Exploring serial vertical interconnects for 3D ICs.	DAC	2009	DBLP DOI BibTeX RDF	serial interconnect, VLSI, networks on chip, 3D ICs
1	Kee Beom Kim, Seong Min Jo, Jin Woo Song, Ki-Seok Chung, Yong Ho Song	Performance evaluation of on-chip interconnect IP using CBR traffic generator model.	ICHIT	2009	DBLP DOI BibTeX RDF	on-chip interconnect IP, simulation, traffic generator
1	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Reactive NUCA: near-optimal block placement and replication in distributed caches.	ISCA	2009	DBLP DOI BibTeX RDF	block migration, block placement, block replication, cache indexing, cache lookup, non-uniform cache access, nuca, r-nuca, reactive nuca, rotational interleaving, cache, replication, chip multiprocessor, cmp, placement, multicore, multi-core, migration, cache coherence, data replication, coherence, interleaving, data migration, data placement, shared cache, cache management, lookup, last-level cache, private cache
1	Zheng Li, Jie Wu, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun	A high-performance low-power nanophotonic on-chip network.	ISLPED	2009	DBLP DOI BibTeX RDF	networks-on-chip, optical communication, silicon photonics
1	Hamid Hajabdolali Bazzaz, Marjan Sirjani, Ramtin Khosravi, Shamim Taheri	Modeling networking issues of network-on-chip: a coloured petri nets approach.	SimuTools	2009	DBLP DOI BibTeX RDF	modeling, network-on-chip, coloured petri nets
1	Tom van den Broek, Julien Schmaltz	Towards a formally verified network-on-chip.	FMCAD	2009	DBLP DOI BibTeX RDF