Search results for "on-chip interconnection networks"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh	Research Challenges for On-Chip Interconnection Networks.	IEEE Micro	2007	DBLP DOI BibTeX RDF	embedded systems, system on chip, network on chip, multicore architectures, on-chip interconnection networks
2	Fadi N. Sibai	Low Diameter Unicast On-Chip Interconnection Networks for Many-Core Embedded Systems.	CISIS	2010	DBLP DOI BibTeX RDF	many core embedded systems, On-chip interconnection networks, network diameter
2	Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri	Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger	On-Chip Interconnection Networks of the TRIPS Chip.	IEEE Micro	2007	DBLP DOI BibTeX RDF	communication, networking, distributed architectures, packet-switching networks, multicore architectures, on-chip interconnection networks
2	Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh	Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	William J. Dally	Enabling Technology for On-Chip Interconnection Networks.	NOCS	2007	DBLP DOI BibTeX RDF
1	Po-Tsang Huang, Wei Hwang	Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks.	J. Electrical and Computer Engineering	2012	DBLP DOI BibTeX RDF
1	Po-Tsang Huang, Wei Hwang	Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Daniel Sanchez, George Michelogiannakis, Christos Kozyrakis	An analysis of on-chip interconnection networks for large-scale chip multiprocessors.	TACO	2010	DBLP DOI BibTeX RDF
1	Minseon Ahn, Eun Jung Kim	Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks.	MICRO	2010	DBLP DOI BibTeX RDF
1	Fadi N. Sibai	Which On-Chip Interconnection Network for 16-core MPSoCs?.	CISIS	2010	DBLP DOI BibTeX RDF	split NoCs, MPSoCs, On-chip interconnection networks, network diameter
1	Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin, Li-Shiuan Peh	Design of a High-Throughput Distributed Shared-Buffer NoC Router.	NOCS	2010	DBLP DOI BibTeX RDF	Router micro-architecture, On-chip interconnection networks
1	Yuho Jin, Eun Jung Kim, Ki Hwan Yum	Design and Analysis of On-Chip Networks for Large-Scale Cache Systems.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	nonuniform cache architecture, domain-specific design, On-chip interconnection networks
1	Samer Damaj, Thierry Goubier, Frédéric Blanc, Bernard Pottier	A Heuristic (delta, D) Digraph to Interpolate between Hypercube and de Bruijn Topologies for Future On-Chip Interconnection Networks.	ICPP Workshops	2009	DBLP DOI BibTeX RDF
1	Chun-Yi Lee, Niraj K. Jha	FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing.	ICCD	2009	DBLP DOI BibTeX RDF
1	Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edward Suh, Marten van Dijk, Srinivas Devadas	Application-aware deadlock-free oblivious routing.	ISCA	2009	DBLP DOI BibTeX RDF	systems-on-chip, oblivious routing, on-chip interconnection networks
1	George L. Yuan, Ali Bakhoda, Tor M. Aamodt	Complexity effective memory access scheduling for many-core accelerator architectures.	MICRO	2009	DBLP DOI BibTeX RDF	graphics processors, on-chip interconnection networks, memory controller
1	Thomas Moscibroda, Onur Mutlu	A case for bufferless routing in on-chip networks.	ISCA	2009	DBLP DOI BibTeX RDF	routing, multi-core, memory systems, on-chip networks
1	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.	The Journal of Supercomputing	2008	DBLP DOI BibTeX RDF	Power dissipation model, Microarchitectural level simulator, Heterogeneus on-chip interconnection network, Chip-multiprocessor, Parallel scientific applications
1	Sun-Yuan Hsieh, Yu-Shu Chen	Strongly Diagnosable Product Networks Under the Comparison Diagnosis Model.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Fault tolerance, modeling, evaluation, Reliability, Measurement, Graph Theory, Graph Theory, Discrete Mathematics, Discrete Mathematics, On-chip interconnection networks, Testing and Fault-Tolerance, Mathematics of Computing, Mathematics of Computing, simulation of multiple-processor systems, Network problems
1	Henrique C. Freitas, Philippe Olivier Alexandre Navaux, Tatiana Gadelha Serra dos Santos	NOC architecture design for multi-cluster chips.	FPL	2008	DBLP DOI BibTeX RDF
1	Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos	Fast arbiters for on-chip network switches.	ICCD	2008	DBLP DOI BibTeX RDF
1	Vaclav Dvorak	Communication Performance of Mesh- and Ring-Based NoCs.	ICN	2008	DBLP DOI BibTeX RDF	Tera-scale platform, Networks on chip, collective communications
1	M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam	Power reduction of CMP communication networks via RF-interconnects.	MICRO	2008	DBLP DOI BibTeX RDF
1	Thomas William Ainsworth, Timothy Mark Pinkston	Characterizing the Cell EIB On-Chip Network.	IEEE Micro	2007	DBLP DOI BibTeX RDF	multiple data stream architectures, multiprocessors, multicore architectures, interconnection architectures, on-chip interconnection networks
1	David Arditti Ilitzky, Jeffrey D. Hoffman, Anthony Chun, Brando Perez Esparza	Architecture of the Scalable Communications Core's Network on Chip.	IEEE Micro	2007	DBLP DOI BibTeX RDF	communication, networking, wireless, parallel architectures, wide-area networks, multicore architectures, on-chip interconnection networks
1	Partha Kundu, Li-Shiuan Peh	Guest Editors' Introduction: On-Chip Interconnects for Multicores.	IEEE Micro	2007	DBLP DOI BibTeX RDF	embedded systems, system on chip, network on chip, multicore architectures, on-chip interconnection networks
1	Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini	Bringing NoCs to 65 nm.	IEEE Micro	2007	DBLP DOI BibTeX RDF	network on chip, low-power design, power management, multicore architectures, on-chip interconnection networks, design aids, deep submicron design
1	David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal	On-Chip Interconnection Architecture of the Tile Processor.	IEEE Micro	2007	DBLP DOI BibTeX RDF	MIMD processors, parallel architectures, mesh networks, multicore architectures, on-chip interconnection networks
1	Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha	Express virtual channels: towards the ideal interconnection fabric.	ISCA	2007	DBLP DOI BibTeX RDF	packet-switching, flow-control, router design
1	William J. Dally	Interconnect-Centric Computing.	HPCA	2007	DBLP DOI BibTeX RDF
1	Guoqiang Yang, Mei Yang, Yulu Yang, Yingtao Jiang	On the Physicl Layout of PRDT-Based NoCs.	ITNG	2007	DBLP DOI BibTeX RDF
1	Vassos Soteriou, Hangsheng Wang, Li-Shiuan Peh	A Statistical Traffic Model for On-Chip Interconnection Networks.	MASCOTS	2006	DBLP DOI BibTeX RDF
1	Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh	Polaris: A System-Level Roadmap for On-Chip Interconnection Networks.	ICCD	2006	DBLP BibTeX RDF
1	James D. Balfour, William J. Dally	Design tradeoffs for tiled CMP on-chip networks.	ICS	2006	DBLP DOI BibTeX RDF
1	Aydin O. Balkan, Gang Qu, Uzi Vishkin	A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing.	ASAP	2006	DBLP DOI BibTeX RDF
1	Carmen Martínez, Enrique Vallejo, Ramón Beivide, Cruz Izu, Miquel Moretó	Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors.	International Journal of Parallel Programming	2006	DBLP DOI BibTeX RDF	lay-out, routing, broadcasting, topology, On-chip networks, circulant graphs
1	Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod	An automated technique for topology and route generation of application specific on-chip interconnection networks.	ICCAD	2005	DBLP BibTeX RDF
1	Hongbing Fan, Yu-Liang Wu	Crossbar based design schemes for switch boxes and programmable interconnection networks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	switch matrix, FPGA, routing, interconnection network, layout, crossbar, switch box
1	Davide Bertozzi, Luca Benini, Giovanni De Micheli	Error control schemes for on-chip communication links: the energy-reliability tradeoff.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González	On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	intercluster communication, instruction steering, complexity, on-chip interconnects, Clustered microarchitecture
1	Aydin O. Balkan, Gang Qu, Uzi Vishkin	Arbitrate-and-move primitives for high throughput on-chip interconnection networks.	ISCAS	2004	DBLP BibTeX RDF
1	Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo	SILENT: serialized low energy transmission coding for on-chip interconnection networks.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Giovanni Beltrame, Gianluca Palermo, Donatella Sciuto, Cristina Silvano	Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs.	CASES	2004	DBLP DOI BibTeX RDF	multiprocessor, network on chip, low-power design, platform based design
1	Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens	A modular simulation framework for architectural exploration of on-chip interconnection networks.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	simulation, network-on-chip, SystemC, architecture exploration
1	Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González, José Duato	Efficient Interconnects for Clustered Microarchitectures.	IEEE PACT	2002	DBLP DOI BibTeX RDF
1	William J. Dally, Brian Towles	Route Packets, Not Wires: On-Chip Interconnection Networks.	DAC	2001	DBLP DOI BibTeX RDF