Search results for "on-chip network"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Seongmoo Heo, Krste Asanovic	Replacing global wires with an on-chip network: a power analysis.	ISLPED	2005	DBLP DOI BibTeX RDF	on-chip network power model, tile size, wire power model, pipelining, router, tiled architecture
2	Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha	GARNET: A detailed on-chip network model inside a full-system simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
2	Zheng Li, Jie Wu, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun	A high-performance low-power nanophotonic on-chip network.	ISLPED	2009	DBLP DOI BibTeX RDF	networks-on-chip, optical communication, silicon photonics
2	Zheng Li, Dan Fay, Alan Rolf Mickelson, Li Shang, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun	Spectrum: a hybrid nanophotonic-electric on-chip network.	DAC	2009	DBLP DOI BibTeX RDF	Networks-on-Chip, optical communication, silicon photonics
2	John Kim	Low-cost router microarchitecture for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	router microarchitecture, complexity, on-chip network
2	Duraid Madina, Makoto Taiji	Circuit and physical design of the MDGRAPE-4 on-chip network links.	SLIP	2008	DBLP DOI BibTeX RDF	capacitive signalling, on-chip network links, periodic routing, quadrature
2	Xu Wang, Ge Gan, Joseph Manzano, Dongrui Fan, Shuxu Guo	A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor.	ICPADS	2008	DBLP DOI BibTeX RDF
2	Thomas William Ainsworth, Timothy Mark Pinkston	Characterizing the Cell EIB On-Chip Network.	IEEE Micro	2007	DBLP DOI BibTeX RDF	multiple data stream architectures, multiprocessors, multicore architectures, interconnection architectures, on-chip interconnection networks
2	Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, An-Yeu Wu	A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network.	NOCS	2007	DBLP DOI BibTeX RDF
2	Hongbo Zeng, Kun Huang, Ming Wu, Weiwu Hu	Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
2	Yuho Jin, Eun Jung Kim, Ki Hwan Yum	A Domain-Specific On-Chip Network Design for Large Scale Cache Systems.	HPCA	2007	DBLP DOI BibTeX RDF
2	Avinoam Kolodny	Networks on chips: keeping up with Rent's rule and Moore's law.	SLIP	2007	DBLP DOI BibTeX RDF	routing, timing, interconnect, power, on-chip network, wires
2	Eui Bong Jung, Han Wook Cho, Neungsoo Park, Yong Ho Song	SONA: An On-Chip Network for Scalable Interconnection of AMBA-Based IPs.	International Conference on Computational Science	2006	DBLP DOI BibTeX RDF
2	Robert D. Mullins, Andrew West, Simon W. Moore	The design and implementation of a low-latency on-chip network.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Chun-Lung Hsu, Chang-Hsin Cheng, Yu-Sheng Huang, Chih-Jung Chen	An Adaptive Low-Power Control Scheme for On-Chip Network Applications.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Jiho Chang, JongSu Yi, JunSeong Kim	A Switch Wrapper Design for SNA On-Chip-Network.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
2	Yuho Jin, Eun Jung Kim, Ki Hwan Yum	Peak Power Control for a QoS Capable On-Chip Network.	ICPP	2005	DBLP DOI BibTeX RDF
2	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski	Reusing an on-chip network for the test of core-based systems.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	TAM and wrapper design, test reuse, network-on-chip, test scheduling, SoC test, Core-based test
2	Andrei Radulescu, John Dielissen, Kees G. W. Goossens, Edwin Rijpkema, Paul Wielage	An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.	DATE	2004	DBLP DOI BibTeX RDF
2	Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu	On Optimal Irregular Switch Box Designs.	FPL	2004	DBLP DOI BibTeX RDF	FPGA, Configurable computing, on-chip network, switch box
1	Shouyi Yin, Yang Hu, Zhen Zhang, Leibo Liu, Shaojun Wei	Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Fadi N. Sibai	A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores.	IEEE Trans. Parallel Distrib. Syst.	2012	DBLP DOI BibTeX RDF
1	Jing Lin, Xiaola Lin, Liang Tang	Making-a-stop: A new bufferless routing algorithm for on-chip network.	J. Parallel Distrib. Comput.	2012	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Memory-Efficient On-Chip Network With Adaptive Interfaces.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	William V. Kritikos, Andrew G. Schmidt, Ron Sass, Erik K. Anderson, Matthew French	Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Jae Young Hur, Todor Stefanov, Stephan Wong, Kees Goossens	Customisation of on-chip network interconnects and experiments in field-programmable gate arrays.	IET Computers & Digital Techniques	2012	DBLP DOI BibTeX RDF
1	Ming-che Lai, Lei Gao, Sheng Ma, Nong Xiao, Zhiying Wang	A practical low-latency router architecture with wing channel for on-chip network.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Somayyeh Koohi, Shaahin Hessabi	Hierarchical opto-electrical on-chip network for future multiprocessor architectures.	Journal of Systems Architecture - Embedded Systems Design	2011	DBLP DOI BibTeX RDF
1	Francesco Bruschi, Antonio Miele, Vincenzo Rana	On-chip network resource management design and validation.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Shan-Jung Miao, Yarsun Hsu	Group allocation: A novel fairness mechanism for on-chip network.	NESEA	2011	DBLP DOI BibTeX RDF
1	Fahimeh Farahnakian, Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila	Q-learning based congestion-aware routing algorithm for on-chip network.	NESEA	2011	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Agent-based on-chip network using efficient selection method.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
1	Gwangsun Kim, John Kim, Sungjoo Yoo	FlexiBuffer: reducing leakage power in on-chip network routers.	DAC	2011	DBLP DOI BibTeX RDF
1	A. Beyranvand Nejad, M. Escudero Martinez, Kees Goossens	An FPGA bridge preserving traffic quality of service for on-chip network-based systems.	DATE	2011	DBLP BibTeX RDF
1	Jason Cong, Yuhui Huang, Bo Yuan	ATree-based topology synthesis for on-chip network.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Minjeong Shin, John Kim	Leveraging torus topology with deadlock recovery for cost-efficient on-chip network.	ICCD	2011	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	High-performance on-chip network platform for memory-on-processor architectures.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Gul N. Khan, Victor Dumitriu	A modeling tool for simulating and design of on-chip network systems.	Microprocessors and Microsystems - Embedded Hardware Design	2010	DBLP DOI BibTeX RDF
1	Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas	A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Radu Stefan, Jason de Windt, Kees G. W. Goossens	On-chip network interfaces supporting automatic burst write creation, posted writes and read prefetch.	ICSAMOS	2010	DBLP DOI BibTeX RDF
1	Hanjoon Kim, Seulki Heo, Junghoon Lee, Jaehyuk Huh, John Kim	On-Chip Network Evaluation Framework.	SC	2010	DBLP DOI BibTeX RDF
1	Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun	Power-efficient variation-aware photonic on-chip network management.	ISLPED	2010	DBLP DOI BibTeX RDF	networks on chip, optical interconnects, nanophotonics
1	Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	A Low-Latency and Memory-Efficient On-chip Network.	NOCS	2010	DBLP DOI BibTeX RDF
1	Ali Bakhoda, John Kim, Tor M. Aamodt	On-chip network design considerations for compute accelerators.	PACT	2010	DBLP DOI BibTeX RDF
1	Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol	An efficient dynamically reconfigurable on-chip network architecture.	DAC	2010	DBLP DOI BibTeX RDF	performance, reconfigurable, topology, power, NoC
1	Majid Janidarmian, Vahhab Samadi Bokharaie, Ahmad Khademzadeh, Misagh Tavanpour	Sorena: New on Chip Network Topology Featuring Efficient Mapping and Simple Deadlock Free Routing Algorithm.	CIT	2010	DBLP DOI BibTeX RDF	routing, mapping, network on chip, topology, deadlock-free
1	Nevin Kirman, José F. Martínez	A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing.	ASPLOS	2010	DBLP DOI BibTeX RDF	wavelength-based oblivious routing, optical network, on-chip network, nanophotonics
1	Alberto Ros, Manuel E. Acacio, José M. García	A Direct Coherence Protocol for Many-Core Chip Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	2010	DBLP DOI BibTeX RDF	Many-core CMP, direct coherence, indirection problem, on-chip network traffic, cache coherence protocol
1	Xiang Zhang, Ahmed Louri	A multilayer nanophotonic interconnection network for on-chip many-core communications.	DAC	2010	DBLP DOI BibTeX RDF	interconnection networks, CMP, 3D, silicon photonics
1	Enric Herrero, José González, Ramon Canal	Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.	ISCA	2010	DBLP DOI BibTeX RDF	elastic cooperative caching, tiled microarchitectures, chip multiprocessors, memory hierarchy
1	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Sri Hari Krishna Narayanan	Compiler directed network-on-chip reliability enhancement for chip multiprocessors.	LCTES	2010	DBLP DOI BibTeX RDF	reliability, compiler, noc, chip multiprocessors
1	Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano	Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IEEE Trans. Parallel Distrib. Syst.	2009	DBLP DOI BibTeX RDF
1	R. Sunkam Ramanujam, B. Lin	A Layer-Multiplexed 3D On-Chip Network Architecture.	Embedded Systems Letters	2009	DBLP DOI BibTeX RDF
1	Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete	Impact of on-chip network parameters on nuca cache performances.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Yu Zhang, Berkin Özisikyilmaz, Gokhan Memik, John Kim, Alok N. Choudhary	Analyzing the impact of on-chip network traffic on program phases for CMPs.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Prabhat Kumar, Yan Pan, John Kim, Gokhan Memik, Alok N. Choudhary	Exploring concentration and channel slicing in on-chip network router.	NOCS	2009	DBLP DOI BibTeX RDF
1	Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick	An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication.	DSD	2009	DBLP DOI BibTeX RDF
1	Rohit Sunkam Ramanujam, Bill Lin	A novel 3D layer-multiplexed on-chip network.	ANCS	2009	DBLP DOI BibTeX RDF
1	Yongqing Ren, Hong An, Ming Cong, Guang Xu, Li Wang	Scaling the Performance of Tiled Processor Architectures with On-Chip-Network Topology.	CSO	2009	DBLP DOI BibTeX RDF
1	Mehdi Modarressi, Hamid Sarbazi-Azad, Mohammad Arjomand	A hybrid packet-circuit switched on-chip network based on SDM.	DATE	2009	DBLP BibTeX RDF
1	Zheng Shi, Alan Burns	Real-Time Communication Analysis with a Priority Share Policy in On-Chip Networks.	ECRTS	2009	DBLP DOI BibTeX RDF	real time communication, on-chip network
1	Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Jun Yang 0002, Li Zhao	Frequent value compression in packet-based NoC architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi	Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency.	DAC	2009	DBLP DOI BibTeX RDF	System-on-Chip, Network-on-Chip, computer architecture
1	Mohammad Hossein Neishaburi, Zeljko Zilic	Reliability aware NoC router architecture using input channel buffer sharing.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	system on chip, network on chip, virtual channel
1	Kee Beom Kim, Seong Min Jo, Jin Woo Song, Ki-Seok Chung, Yong Ho Song	Performance evaluation of on-chip interconnect IP using CBR traffic generator model.	ICHIT	2009	DBLP DOI BibTeX RDF	on-chip interconnect IP, simulation, traffic generator
1	Mohammad Arjomand, Hamid Sarbazi-Azad	A comprehensive power-performance model for NoCs with multi-flit channel buffers.	ICS	2009	DBLP DOI BibTeX RDF	performance, network-on-chip, power, analytical modeling, queuing system
1	Yan Pan, Prabhat Kumar, John Kim, Gokhan Memik, Yu Zhang, Alok N. Choudhary	Firefly: illuminating future network-on-chip with nanophotonics.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, topology, hierarchical network, nanophotonics
1	Boris Grot, Stephen W. Keckler, Onur Mutlu	Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip.	MICRO	2009	DBLP DOI BibTeX RDF
1	Mitchell Hayenga, Natalie D. Enright Jerger, Mikko H. Lipasti	SCARAB: a single cycle adaptive routing and bufferless network.	MICRO	2009	DBLP DOI BibTeX RDF	routing, interconnection networks, multi-core
1	Gul N. Khan, Victor Dumitriu	Throughput-based network-on-chip topology generation and analysis.	CCECE	2009	DBLP DOI BibTeX RDF
1	Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell	Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.	HPCA	2009	DBLP DOI BibTeX RDF
1	Aditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Sri Hari Krishna Narayanan	In-Network Caching for Chip Multiprocessors.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Hazem Moussa, Amer Baghdadi, Michel Jézéquel	Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder.	DAC	2008	DBLP DOI BibTeX RDF	flexible LDPC decoder, multiprocessor, NoC, de Bruijn graph
1	Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete	Performance Sensitivity of NUCA Caches to On-Chip Network Parameters.	SBAC-PAD	2008	DBLP DOI BibTeX RDF
1	Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos	Fast arbiters for on-chip network switches.	ICCD	2008	DBLP DOI BibTeX RDF
1	Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian	Scalable and reliable communication for hardware transactional memory.	PACT	2008	DBLP DOI BibTeX RDF	algorithms for transaction commit, handling message loss, on-chip network messages, token coherence, reliability, hardware transactional memory
1	Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston	A Lightweight Fault-Tolerant Mechanism for Network-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF	fault tolerance, reliability, Network-on-Chip, routing algorithm, deadlock avoidance, on-chip network
1	Woo-Cheol Kwon, Sungjoo Yoo, Sung-Min Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo	A practical approach of memory access parallelization to exploit multiple off-chip DDR memories.	DAC	2008	DBLP DOI BibTeX RDF	parallelization, memory, arbitration
1	Ahmed A. Morgan, Haytham Elmiligi, M. Watheq El-Kharashi, Fayez Gebali	Application-specific networks-on-chip topology customization using network partitioning.	IFMT	2008	DBLP DOI BibTeX RDF	application-specific networks-on-chip (ASNoC), core graph, optimization, analysis, topology, network partitioning
1	Jeffrey R. Diamond, Behnam Robatmili, Stephen W. Keckler, Robert A. van de Geijn, Kazushige Goto, Doug Burger	High performance dense linear algebra on a spatially distributed processor.	PPOPP	2008	DBLP DOI BibTeX RDF	gotoblas, grid processors, hybrid dataflow, matrix multiply, tile based architecture, instruction level parallelism, on-chip networks, dense linear algebra
1	Wim Heirman, Joni Dambre, Dirk Stroobandt, Jan M. Van Campenhout	Rent's rule and parallel programs: characterizing network traffic behavior.	SLIP	2008	DBLP DOI BibTeX RDF	network traffic behavior, locality, network-on-chip, characterization, Rent's rule
1	Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen	Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, systems on chips, networks on chip, interconnection, Application specific
1	Woo-Cheol Kwon, Sung-Min Hong, Sungjoo Yoo, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo	An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication.	DATE	2008	DBLP DOI BibTeX RDF
1	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Multicast Parallel Pipeline Router Architecture for Network-on-Chip.	DATE	2008	DBLP DOI BibTeX RDF
1	Feng Yuan, Lin Huang, Qiang Xu	Re-Examining the Use of Network-on-Chip as Test Access Mechanism.	DATE	2008	DBLP DOI BibTeX RDF
1	Byung-Gyu Ahn, Jun-Mo Jung, Jong-Wha Chong	Power-Aware Test Framework for Network-on-Chip.	ICONS	2008	DBLP DOI BibTeX RDF	test, low-power, NoC
1	Andres Mejia, Jose Flich, José Duato	On the Potentials of Segment-Based Routing for NoCs.	ICPP	2008	DBLP DOI BibTeX RDF
1	Amit Kumar 0002, Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha	A system-level perspective for efficient NoC design.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Hongbo Zeng, Jun Wang, Ge Zhang, Weiwu Hu	An interconnect-aware power efficient cache coherence protocol for CMPs.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Xin Wang, Jari Nurmi	Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin	Leakage-Aware Interconnect for On-Chip Network	CoRR	2007	DBLP BibTeX RDF
1	Arun Janarthanan, Vijay Swaminathan, Karen A. Tomko	MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano	Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Ik-Jae Chun, Tae Moon Roh, Bo-Gwan Kim	Binary-Truncated CDMA-Based On-Chip Network.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Thomas William Ainsworth, Timothy Mark Pinkston	On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus.	NOCS	2007	DBLP DOI BibTeX RDF	Element Interconnect Bus, heterogeneous multicore, network characterization, interconnection networks, network-on-chip, Cell Broadband Engine, on-chip network, performance bottleneck
1	Hong Xiao, Di Wu	A Component Model for Network Processor Based System.	AICCSA	2007	DBLP DOI BibTeX RDF
1	Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha	A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS.	ICCD	2007	DBLP DOI BibTeX RDF
1	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede	Analytical modelling of communication in the rectangular mesh NoC.	ICPADS	2007	DBLP DOI BibTeX RDF
1	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.	MICRO	2007	DBLP DOI BibTeX RDF	non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models
1	Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy, Rajaraman Ramanarayanan, Balaji Vaidyanathan	A Process Scheduler-Based Approach to NoC Power Management.	VLSI Design	2007	DBLP DOI BibTeX RDF