Search results for "on-chip networks"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Thomas Moscibroda, Onur Mutlu	A case for bufferless routing in on-chip networks.	ISCA	2009	DBLP DOI BibTeX RDF	routing, multi-core, memory systems, on-chip networks
3	Li Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha	Temperature-Aware On-Chip Networks.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Temperature-aware, thermal management, thermal modeling, on-chip networks, thermal, simulation framework
3	Sudarshan Banerjee, Nikil D. Dutt	FIFO power optimization for on-chip networks.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	wide flits, low power design, shared memory, switches, FIFO, on-chip networks
2	Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das	Aérgia: exploiting packet latency slack in on-chip networks.	ISCA	2010	DBLP DOI BibTeX RDF	multi-core, packet scheduling, memory systems, arbitration, prioritization, on-chip networks
2	George Michelogiannakis, William J. Dally	Router designs for elastic buffer on-chip networks.	SC	2009	DBLP DOI BibTeX RDF	on-chip networks
2	Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das	Application-aware prioritization mechanisms for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	multi-core, packet scheduling, memory systems, arbitration, prioritization, on-chip networks
2	John Kim	Low-cost router microarchitecture for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	router microarchitecture, complexity, on-chip network
2	Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Keng-Hsien Huang, An-Yeu Wu	Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano	Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.	NOCS	2008	DBLP DOI BibTeX RDF	low power, Network-on-Chip, virtual channels, NoC, DVFS, power gating
2	Alireza Ejlali, Bashir M. Al-Hashimi	SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks.	NOCS	2008	DBLP DOI BibTeX RDF
2	Jwo-An Lin, Yung-Chou Tsai, Tay-Jyi Lin, Yarsun Hsu	Cycle Stealing and Channel Management for On-Chip Networks.	HPCC	2008	DBLP DOI BibTeX RDF
2	John Kim, James D. Balfour, William J. Dally	Flattened Butterfly Topology for On-Chip Networks.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
2	John Kim, James D. Balfour, William J. Dally	Flattened Butterfly Topology for On-Chip Networks.	MICRO	2007	DBLP DOI BibTeX RDF
2	Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi	Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks.	DATE	2007	DBLP DOI BibTeX RDF
2	Byungsub Kim, Vladimir Stojanovic	Equalized interconnects for on-chip networks: modeling and optimization framework.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park	A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.	ISCA	2006	DBLP DOI BibTeX RDF
2	James D. Balfour, William J. Dally	Design tradeoffs for tiled CMP on-chip networks.	ICS	2006	DBLP DOI BibTeX RDF
2	Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli	A robust self-calibrating transmission scheme for on-chip networks.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Hangsheng Wang, Li-Shiuan Peh, Sharad Malik	A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks.	DATE	2005	DBLP DOI BibTeX RDF
2	Li Shang, Li-Shiuan Peh, Amit Kumar 0002, Niraj K. Jha	Thermal Modeling, Characterization and Management of On-Chip Networks.	MICRO	2004	DBLP DOI BibTeX RDF
2	Noel Eisley, Li-Shiuan Peh	High-level power analysis for on-chip networks.	CASES	2004	DBLP DOI BibTeX RDF	simulation, power analysis, systems-on-a-chip (SoC), link utilization
2	Hangsheng Wang, Li-Shiuan Peh, Sharad Malik	Power-driven Design of Router Microarchitectures in On-chip Networks.	MICRO	2003	DBLP DOI BibTeX RDF
2	Girish Varatkar, Radu Marculescu	Traffic analysis for on-chip networks design of multimedia applications.	DAC	2002	DBLP DOI BibTeX RDF	self-similarity, system-level design, long-range dependence, on-chip networks, communication analysis
1	Yuho Jin, Eun Jung Kim, Timothy Mark Pinkston	Communication-Aware Globally-Coordinated On-Chip Networks.	IEEE Trans. Parallel Distrib. Syst.	2012	DBLP DOI BibTeX RDF
1	Angelo Kuti Lusala, Jean-Didier Legat	Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun	Reliability Modeling and Management of Nanophotonic On-Chip Networks.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Andreas G. Savva, Theocharis Theocharides, Vassos Soteriou	Intelligent On/Off Dynamic Link Management for On-Chip Networks.	J. Electrical and Computer Engineering	2012	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks.	DATE	2012	DBLP BibTeX RDF
1	Giorgos Dimitrakopoulos, Emmanouil Kalligeros	Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches.	DATE	2012	DBLP BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	LEAR - A Low-Weight and Highly Adaptive Routing Method for Distributing Congestions in On-chip Networks.	PDP	2012	DBLP DOI BibTeX RDF
1	Kun-Chih Chen, Shu-Yen Lin, Wen-Chung Shen, An-Yeu Wu	A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks.	Design Autom. for Emb. Sys.	2011	DBLP DOI BibTeX RDF
1	George Michelogiannakis, Nan Jiang, Daniel U. Becker, William J. Dally	Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks.	Computer Architecture Letters	2011	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das	RAFT: A router architecture with frequency tuning for on-chip networks.	J. Parallel Distrib. Comput.	2011	DBLP DOI BibTeX RDF
1	Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad	Application-Aware Topology Reconfiguration for On-Chip Networks.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Saeed Shamshiri, Amirali Ghofrani, Kwang-Ting Cheng	End-to-end error correction and online diagnosis for on-chip networks.	ITC	2011	DBLP DOI BibTeX RDF
1	Andreas G. Savva, Theocharis Theocharides, Vassos Soteriou	Intelligent On/Off Link Management for On-chip Networks.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Nasibeh Teimouri, Mehdi Modarressi, Arash Tavakkol, Hamid Sarbazi-Azad	Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths.	ARCS	2011	DBLP DOI BibTeX RDF
1	Son Truong Nguyen, Shigeru Oyanagi	An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation.	ARCS	2011	DBLP DOI BibTeX RDF
1	Christopher Nitta, Kevin Macdonald, Matthew K. Farrens, Venkatesh Akella	Inferring packet dependencies to improve trace based simulation of on-chip networks.	NOCS	2011	DBLP BibTeX RDF
1	Junghoon Lee, Minjeong Shin, Hanjoon Kim, John Kim, Jaehyuk Huh	Exploiting Mutual Awareness between Prefetchers and On-chip Networks in Multi-cores.	PACT	2011	DBLP DOI BibTeX RDF
1	Masashi Imai, Tomohiro Yoneda	Improving Dependability and Performance of Fully Asynchronous On-chip Networks.	ASYNC	2011	DBLP DOI BibTeX RDF
1	George Michelogiannakis, Nan Jiang, Daniel U. Becker, William J. Dally	Packet chaining: efficient single-cycle allocation for on-chip networks.	MICRO	2011	DBLP DOI BibTeX RDF
1	Zheng Li, Moustafa Mohamed, Xi Chen, Alan Rolf Mickelson, Li Shang	Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance.	DAC	2011	DBLP DOI BibTeX RDF
1	Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato	A Distributed Switch Architecture for On-Chip Networks.	ICPP	2011	DBLP DOI BibTeX RDF	switch implementation, network-on-chip
1	Amirali Habibi, Mohammad Arjomand, Hamid Sarbazi-Azad	Multicast-Aware Mapping Algorithm for On-chip Networks.	PDP	2011	DBLP DOI BibTeX RDF
1	Fahimeh Jafari, Axel Jantsch, Zhonghai Lu	Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling.	ICCD	2011	DBLP DOI BibTeX RDF
1	Angelo Kuti Lusala, Jean-Didier Legat	A SDM-TDM based circuit-switched router for on-chip networks.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Efficient congestion-aware selection method for on-chip networks.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Yuho Jin, Eun Jung Kim, Ki Hwan Yum	Design and Analysis of On-Chip Networks for Large-Scale Cache Systems.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	nonuniform cache architecture, domain-specific design, On-chip interconnection networks
1	Wei Hu, Tianzhou Chen, Qingsong Shi, Sha Liu	Critical-Path Driven Routers for on-Chip Networks.	Journal of Circuits, Systems, and Computers	2010	DBLP DOI BibTeX RDF
1	Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi, Luca Benini	Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Radu Marculescu	On-chip networks: Two sides of the same coin.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF
1	Antoni Roca, José Flich, Federico Silla, José Duato	VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks.	HiPC	2010	DBLP DOI BibTeX RDF
1	Esteban Stafford, José Luis Bosque, Carmen Martínez, Fernando Vallejo, Ramón Beivide, Cristobal Camarero	A First Approach to King Topologies for On-Chip Networks.	Euro-Par	2010	DBLP DOI BibTeX RDF
1	Hsin-Chou Chi, Yu-Hong Jhang, Wen-Shu Chen	Tree-Based Routing for Faulty On-Chip Networks with Mesh Topology.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Sargis Abovyan, Gor Petrosyan, Tigran Harutyunyan	Architecture of queued-free crossbar for on-chip networks.	EWDTS	2010	DBLP DOI BibTeX RDF
1	George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu	Next generation on-chip networks: what kind of congestion control do we need?	HotNets	2010	DBLP DOI BibTeX RDF
1	George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis	Evaluating Bufferless Flow Control for On-chip Networks.	NOCS	2010	DBLP DOI BibTeX RDF	Networks, Flow control, Buffers, Multiprocessor interconnection
1	Andreas Lankes, Thomas Wild, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig	Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks.	NOCS	2010	DBLP DOI BibTeX RDF	message dependent deadlocks, strict ordering, Network-on-chip, deadlock avoidance, deadlock recovery
1	Young Hoon Kang, Taek-Jun Kwon, Jeffrey T. Draper	Fault-Tolerant Flow Control in On-chip Networks.	NOCS	2010	DBLP DOI BibTeX RDF	fault-tolerant router, soft-error handling, networks-on-chip
1	Jonas Diemer, Rolf Ernst	Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks.	NOCS	2010	DBLP DOI BibTeX RDF	Latency-Sensitive, Quality of Service, QoS, Real-Time, NoC, Manycore
1	Son Truong Nguyen, Shigeru Oyanagi	A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks.	DSD	2010	DBLP DOI BibTeX RDF
1	Michael M. Lee, John Kim, Dennis Abts, Michael R. Marty, Jae W. Lee	Approximating age-based arbitration in on-chip networks.	PACT	2010	DBLP DOI BibTeX RDF
1	Matthew Misler, Natalie D. Enright Jerger	Moths: mobile threads for on-chip networks.	PACT	2010	DBLP DOI BibTeX RDF
1	Ali Bakhoda, John Kim, Tor M. Aamodt	Throughput-Effective On-Chip Networks for Manycore Accelerators.	MICRO	2010	DBLP DOI BibTeX RDF
1	Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King, Shau-Yin Tseng	NTPT: on the end-to-end traffic prediction in the on-chip networks.	DAC	2010	DBLP DOI BibTeX RDF	end-to-end traffic prediction, network-on-chip, many-core
1	Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi	Configurable fault-tolerant link for inter-die communication in 3D on-chip networks.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan	Optimizing power and performance for reliable on-chip networks.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Wei Song 0002, Doug Edwards	A low latency wormhole router for asynchronous on-chip networks.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Hsin-Chou Chi, Tat-Seng Chang, Chia-Ming Wu	Design of a Reconfigurable Pipelined Switch for Faulty On-Chip Networks.	SIES	2010	DBLP DOI BibTeX RDF
1	Andrew G. Schmidt, William V. Kritikos, Ron Sass, Erik K. Anderson, Matthew French	Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core Systems on a Programmable Chip.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Angelo Kuti Lusala, Jean-Didier Legat	A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian	Towards scalable, energy-efficient, bus-based on-chip networks.	HPCA	2010	DBLP DOI BibTeX RDF
1	Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi	Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs.	NOCS	2010	DBLP DOI BibTeX RDF	asynchronous interconnect, NoC, GALS, on-chip networks
1	Yue Qian, Zhonghai Lu, Wenhua Dou, Qiang Dou	Analyzing Credit-Based Router-to-Router Flow Control for On-Chip Networks.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Natalie D. Enright Jerger, Li-Shiuan Peh	On-Chip Networks		2009	DOI RDF
1	Arnab Banerjee, Simon W. Moore	Flow-aware allocation for on-chip networks.	NOCS	2009	DBLP DOI BibTeX RDF
1	Wei Song 0002, Doug Edwards, Jose Luis Nunez-Yanez, Sohini Dasgupta	Adaptive stochastic routing in fault-tolerant on-chip networks.	NOCS	2009	DBLP DOI BibTeX RDF
1	Alexander Wei Yin, Liang Guang, Ethiopia Nigussie, Pasi Liljeberg, Jouni Isoaho, Hannu Tenhunen	Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks.	DSD	2009	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das	A case for dynamic frequency tuning in on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF
1	Zheng Shi, Alan Burns	Real-Time Communication Analysis with a Priority Share Policy in On-Chip Networks.	ECRTS	2009	DBLP DOI BibTeX RDF	real time communication, on-chip network
1	George Michelogiannakis, James D. Balfour, William J. Dally	Elastic-buffer flow control for on-chip networks.	HPCA	2009	DBLP DOI BibTeX RDF
1	Ajay Joshi, Byungsub Kim, Vladimir Stojanovic	Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects.	Hot Interconnects	2009	DBLP DOI BibTeX RDF
1	Yue Qian, Zhonghai Lu, Wenhua Dou	Applying network calculus for performance analysis of self-similar traffic in on-chip networks.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	performance analysis, network-on-chip, network calculus, self-similar traffic
1	Ian Gray, Neil C. Audsley	Exposing non-standard architectures to embedded software using compile-time virtualisation.	CASES	2009	DBLP DOI BibTeX RDF	architectures, virtualization, embedded, application-specific, compile-time
1	Andreas Hansson, Kees Goossens	An on-chip interconnect and protocol stack for multiple communication paradigms and programming models.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	system on chip, network on chip, programming model, protocol stack
1	Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper	Multicast routing with dynamic packet fragmentation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	on-chip router, interconnection network, NoC
1	Mohammad Hossein Neishaburi, Zeljko Zilic	Reliability aware NoC router architecture using input channel buffer sharing.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	system on chip, network on chip, virtual channel
1	Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar	Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	vlsi design, task allocation, multiprocessor systems-on-chip
1	Yan Pan, Prabhat Kumar, John Kim, Gokhan Memik, Yu Zhang, Alok N. Choudhary	Firefly: illuminating future network-on-chip with nanophotonics.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, topology, hierarchical network, nanophotonics
1	Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha	In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects.	HPCA	2009	DBLP DOI BibTeX RDF
1	Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio	MRR: Enabling fully adaptive multicast routing for CMP interconnection networks.	HPCA	2009	DBLP DOI BibTeX RDF
1	Amlan Ganguly, Kevin Chang, Partha Pratim Pande, Benjamin Belzer, Alireza Nojeh	Performance evaluation of wireless networks on chip architectures.	ISQED	2009	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano	Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network.	IEEE Trans. Parallel Distrib. Syst.	2009	DBLP DOI BibTeX RDF
1	José L. Núñez-Yáñez, Doug Edwards, Antonio Marcello Coppola	Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems.	IET Computers & Digital Techniques	2008	DBLP DOI BibTeX RDF
1	Martha Mercaldi Kim, John D. Davis, Mark Oskin, Todd M. Austin	Polymorphic On-Chip Networks.	ISCA	2008	DBLP DOI BibTeX RDF
1	Jae W. Lee, Man Cheuk Ng, Krste Asanovic	Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks.	ISCA	2008	DBLP DOI BibTeX RDF
1	Ting-Jung Lin, Shu-Yen Lin, An-Yeu Wu	Traffic-balanced IP mapping algorithm for 2D-mesh On-Chip-Networks.	SiPS	2008	DBLP DOI BibTeX RDF
1	Piotr Dziurzanski, Tomasz Maka	Heuristics Core Mapping in On-Chip Networks for Parallel Stream-Based Applications.	ICCS	2008	DBLP DOI BibTeX RDF	Multimedia streaming applications, On-Chip routing algorithm, IP core mapping, Multi-path routing
1	Zheng Shi, Alan Burns	Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching.	NOCS	2008	DBLP DOI BibTeX RDF	real-time, schedulable analysis, wormhole switching