Search results for "on-line testing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Alexander V. Drozd, M. V. Lobachev, J. V. Drozd	The Problem of On-Line Testing Methods In Approximate Data Processing.	IOLTS	2006	DBLP DOI BibTeX RDF
3	Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Deepali Koppad	On-Line Testing of Globally Asynchronous Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF
3	Vinay Verma, Shantanu Dutt, Vishal Suthar	Efficient on-line testing of FPGAs with provable diagnosabilities.	DAC	2004	DBLP DOI BibTeX RDF	built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
3	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Low Cost On-Line Testing of RF Circuits.	IOLTS	2004	DBLP DOI BibTeX RDF
3	Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra	Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits.	IOLTS	2004	DBLP DOI BibTeX RDF
3	Mohammad A. Naal, Emmanuel Simeu, Salvador Mir	On-Line Testable Decimation Filter Design for AMS Systems. (PDF / PS)	IOLTS	2003	DBLP DOI BibTeX RDF	non-concurrent, semi-concurrent, SigmaDelta, decimation filters, analogue BIST, on-line testing
3	Mohammad A. Naal, M. Rakotoar, Emmanuel Simeu, Chouki Aktouf	Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable Approach.	IOLTW	2002	DBLP DOI BibTeX RDF
3	Naotake Kamiura, Kazuharu Yamato, Teijiro Isokawa, Nobuyuki Matsui	Learning-Based On-Line Testing in Feedforward Neural Networks.	IOLTW	2002	DBLP DOI BibTeX RDF
3	Y. Maidon, Yann Deval, Jean-Baptiste Begueret	An Improved CMOS BICS for On-Line Testing.	IOLTW	2000	DBLP DOI BibTeX RDF	On Line Testing, IDDQ testing, Built-In Current Sensor
3	Michael Nicolaidis, Yervant Zorian	On-Line Testing for VLSI - A Compendium of Approaches.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	fail-safe circuits, SEU hardened circuits, monitoring of reliability indicators, thermal monitors, radiation monitors, on-line testing, self-checking circuits, current monitors
3	Serge N. Demidenko, Vincenzo Piuri	On-Line Testing In Digital Neural Networks.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	digital neural networks, concurrent fault-tolerance policy, error localisation, system survival, concurrent diagnosis, data coding, neuron level error detection, on-line localisation, faulty neuron, multilayer feedforward networks, synaptic errors, summation errors, architecture regularity, automatic reconfiguration, fault tolerant computing, fault model, on-line testing, signature analysis, arithmetic codes, residue codes, hardware reconfiguration
2	Anna Vaskova, Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena	Evaluation techniques for on-line testing of robust systems based on critical tasks distribution.	IOLTS	2011	DBLP DOI BibTeX RDF
2	Paolo Bernardi, Lyl M. Ciganda, Ernesto Sánchez, Matteo Sonza Reorda	An effective methodology for on-line testing of embedded microprocessors.	IOLTS	2011	DBLP DOI BibTeX RDF
2	Michael G. Dimopoulos, Alexios Spyronasios, Alkis A. Hatzopoulos	Wavelet analysis of measurements for on-line testing analog & mixed-signal circuits.	IOLTS	2010	DBLP DOI BibTeX RDF
2	Steffen Zeidler, Alexandre V. Bystrov, Milos Krstic, Rolf Kraemer	On-line testing of bundled-data asynchronous handshake protocols.	IOLTS	2010	DBLP DOI BibTeX RDF
2	Olivier Ginez, Jean Michel Portal, Hassen Aziza	An on-line testing scheme for repairing purposes in Flash memories.	DDECS	2009	DBLP DOI BibTeX RDF
2	Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche	Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.	European Test Symposium	2008	DBLP DOI BibTeX RDF	microprocessor, error detecting codes, on-line testing, control logic
2	Nachiketa Das, Pranab Roy, Hafizur Rahaman	On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous Element.	IOLTS	2008	DBLP DOI BibTeX RDF
2	Yang Zhao, Krishnendu Chakrabarty	On-Line Testing of Lab-on-Chip Using Digital Microfluidic Compactors.	IOLTS	2008	DBLP DOI BibTeX RDF
2	Andreas Merentitis, George Theodorou, Mihalis Giorgaras, Nektarios Kranitis	Directed Random SBST Generation for On-Line Testing of Pipelined Processors.	IOLTS	2008	DBLP DOI BibTeX RDF
2	Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak	Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation.	IOLTS	2006	DBLP DOI BibTeX RDF
2	Marcelo de Souza Moraes, Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski	A constraint-based solution for on-line testing of processors embedded in real-time applications.	SBCCI	2005	DBLP DOI BibTeX RDF	test space exploration, real-time systems, embedded processors, on-line testing, software-based self-test
2	Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar	On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Recovery During Concurrent On-Line Testing of Identical Circuits.	DFT	2005	DBLP DOI BibTeX RDF
2	Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert	On-Line Testing for Secure Implementations: Design and Validation.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Kentaroh Katoh, Abderrahim Doumar, Hideo Ito	Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Andrzej Krasniewski	A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Haibo Wang, Suchitra Kulkarni, Spyros Tragoudas	On-line Testing Field Programmable Analog Array Circuits.	ITC	2004	DBLP DOI BibTeX RDF
2	Alexander V. Drozd, R. Al-Azzeh, J. V. Drozd, M. V. Lobachev	The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated Data.	DSD	2004	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines.	DFT	2004	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors.	DFT	2004	DBLP DOI BibTeX RDF
2	V. Agarwal	A Pragmatic Approach to On-Line Testing. (PDF / PS)	IOLTS	2004	DBLP DOI BibTeX RDF
2	Cecilia Metra, A. Ferrari, Martin Omaña, Andrea Pagni	Hardware Reconfiguration Scheme for High Availability Systems.	IOLTS	2004	DBLP DOI BibTeX RDF
2	A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky	A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations.	IOLTS	2004	DBLP DOI BibTeX RDF
2	Nikolaos G. Bartzoudis, Alexandros G. Fragkiadakis, David J. Parish, Jose Luis Nunez	A System for Fault Detection and Reconfiguration of Hardware Based Active Networks.	IOLTS	2004	DBLP DOI BibTeX RDF	Reconfigurable Computing, Active Networks, On-line Testing, System Security
2	Yi Zhao, Sujit Dey	Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC.	IOLTS	2003	DBLP DOI BibTeX RDF
2	Bartomeu Alorda, Jaume Segura	An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing.	IOLTS	2003	DBLP DOI BibTeX RDF	Current based testing, off-chip current monitors, built-in current monitors, power grid modeling, transient current
2	George Xenoulis, Dimitris Gizopoulos, Nektarios Kranitis, Antonis M. Paschalis	Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores.	IOLTS	2003	DBLP DOI BibTeX RDF
2	Yi Zhao, Li Chen, Sujit Dey	On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips.	ITC	2002	DBLP DOI BibTeX RDF
2	Cecilia Metra, Stefano Di Francescantonio, T. M. Mak	Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing.	ITC	2002	DBLP DOI BibTeX RDF
2	Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli	Self-Checking Scheme for the On-Line Testing of Power Supply Noise.	DATE	2002	DBLP DOI BibTeX RDF
2	Petros Oikonomakos, Mark Zwolinski	Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment.	IOLTW	2002	DBLP DOI BibTeX RDF
2	Chouki Aktouf, Benoît Pannetier, Pierre Lemaître-Auger, Smail Tedjini	On-line Testing of Embedded Systems Using Optical Probes: System Modeling and Probing Technology. (PDF / PS)	IOLTW	2002	DBLP DOI BibTeX RDF
2	Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis	A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing.	IOLTW	2002	DBLP DOI BibTeX RDF
2	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	IOLTW	2002	DBLP DOI BibTeX RDF
2	Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira	Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing.	IOLTW	2002	DBLP DOI BibTeX RDF
2	Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.	Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Speech-Recognition Systems (SRS), Recovery Blocks Scheme, Digital Signal Processing (DSP), On-Line Testing, Performance Degradation, Noise Immunity
2	Cecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò	On-Chip Clock Faults' Detector.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	clock faults, systems-on-a-chip, on-line testing
2	Octavian Petre, Hans G. Kerkhoff	Increasing the Fault Coverage in Multiple Clock Domain Systems by Using On-Line Testing of Synchronizers.	IOLTW	2001	DBLP DOI BibTeX RDF
2	Chouki Aktouf	On-Line Testing in Continuous Operation of Embedded Systems: Modeling and Performance Evaluation. (PDF / PS)	IOLTW	2001	DBLP DOI BibTeX RDF
2	Zan Yang, Gwan Choi	An On-Line Testing Approach Using Code-Perturbation. (PDF / PS)	IOLTW	2001	DBLP DOI BibTeX RDF
2	Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir	Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.	IOLTW	2001	DBLP DOI BibTeX RDF
2	Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John M. Emmert	Improving On-Line BIST-Based Diagnosis for Roving STARs.	IOLTW	2000	DBLP DOI BibTeX RDF	on-line testing and diagnosis, FPGA test and diagnosis
2	Vincent Pouget, Pascal Fouillat, Dean Lewis, Hervé Lapuyade, L. Sarger, F. M. Roche, S. Duzellier, R. Ecoffet	An Overview of the Applications of a Pulsed Laser System for SEU Testing.	IOLTW	2000	DBLP DOI BibTeX RDF
2	Jaime Velasco-Medina, Marcelo Lubaszewski, Michael Nicolaidis	An Approach to the On-Line Testing of Operational Amplifiers.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
2	Diego Vázquez, Adoración Rueda, José L. Huertas	A solution for the on-line test of analog ladder filters.	VTS	1995	DBLP DOI BibTeX RDF	ladder filters, analog ladder filters, stability problems, design for test methodology, solution feasibility, analogue ICs, integrated circuit testing, design for testability, on-line testing, analogue integrated circuits, active filters, active filters, circuit stability
1	Cecilia Metra, Rajesh Galivanche	Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Gilles Fritz, Vincent Beroulle, Oum-El-Kheir Aktouf, Minh Duc Nguyen, David Hély	RFID System On-line Testing Based on the Evaluation of the Tags Read-Error-Rate.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	George Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos	A Software-Based Self-Test methodology for on-line testing of processor caches.	ITC	2011	DBLP DOI BibTeX RDF
1	Alexander Drozd, Svetlana Antoshchuk	New on-line testing methods for approximate data processing in the computing circuits.	IDAACS	2011	DBLP DOI BibTeX RDF
1		17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece	IOLTS	2011	DBLP BibTeX RDF
1	Rance Rodrigues, Sandip Kundu	On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Osnat Keren, Ilya Levin, Vladimir Sinelnikov	Detection of Trojan HW by using hidden information on the system.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme	Generalized parity-check matrices for SEC-DED codes with fixed parity.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Rshdee Alhakim, Emmanuel Simeu, Kosai Raoof	Internal model control for a self-tuning Delay-Locked Loop in UWB communication systems.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Daniel Sánchez, Yiannakis Sazeides, Juan L. Aragón, Joso M. Garcia	An analytical model for the calculation of the Expected Miss Ratio in faulty caches.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Jayaram Natarajan, Shreyas Sen, Abhijit Chatterjee	Real time cross-layer adaptation for minimum energy wireless image transport using bit error rate control.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Aymen Fradi, Michael Nicolaidis, Lorena Anghel	Memory BIST with address programmability.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Nivard Aymerich, A. Asenov, A. Brown, Ramon Canal, B. Cheng, Joan Figueras, Antonio González, Enric Herrero, S. Markov, Miguel Miranda, P. Pouyan, Tanausu Ramirez, Antonio Rubio, I. Vatajelu, Xavier Vera, X. Wang, Paul Zuber	New reliability mechanisms in memory design for sub-22nm technologies.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Gabriele Boschi, Riccardo Mariani, Stefano Lorenzini	A verification strategy for fault-detection and fault-tolerance circuits.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Armin Krieg, Johannes Grinschgl, Christian Steger, Reinhold Weiss, Josef Haid	A side channel attack countermeasure using system-on-chip power profile scrambling.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Mikhail Baklashov	An on-line memory state validation using shadow memory cloning.	IOLTS	2011	DBLP DOI BibTeX RDF
1	V. Prasanth, Virendra Singh, Rubin A. Parekhji	Reduced overhead soft error mitigation using error control coding techniques.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Jorge O. M. Esteves, Tiago H. Moita, Carlos B. Almeida, Marcelino B. dos Santos	ICT: Interface software for the characterization and test of mixed-signal power cores.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Aravind Rajendran, Yuriy Shiyanovskii, Frank Wolff, Christos A. Papachristou	Noise margin, critical charge and power-delay tradeoffs for SRAM design.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Luke Pierce, Spyros Tragoudas	Multi-level secure JTAG architecture.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Anna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena	Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Jaume Abella, Francisco J. Cazorla, Eduardo Quiñones, Arnaud Grasset, Sami Yehia, Philippe Bonnot, Dimitris Gizopoulos, Riccardo Mariani, Guillem Bernat	Towards improved survivability in safety-critical systems.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Taiki Uemura, Takashi Kato, Hideya Matsuyama, Keiji Takahisa, Mitsuhiro Fukuda, Kichiji Hatanaka	Investigation of multi cell upset in sequential logic and validity of redundancy technique.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides	RVC-based time-predictable faulty caches for safety-critical systems.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Yuriy Shiyanovskii, Aravind Rajendran, Christos A. Papachristou	A novel radiation tolerant SRAM design based on synergetic functional component separation for nanoscale CMOS.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Seyab Khan, Said Hamdioui	Modeling and mitigating NBTI in nanoscale circuits.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Chiara Sandionigi, Luca Fossati, David Merodio Codinachs	A reliable fault classifier for dependable systems on SRAM-based FPGAs.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Michael Augustin, Michael Gössel, Rolf Kraemer	Selective fault tolerance for finite state machines.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Taiga Takata, Yusuke Matsunaga	A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Eberhard Böhl, Paul Duplys	Fault attack resistant deterministic random bit generator usable for key randomization.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara	High-level synthesis for multi-cycle transient fault tolerant datapaths.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov	Self-checking test circuits for latches and flip-flops.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Dan Alexandrescu	A comprehensive soft error analysis methodology for SoCs/ASICs memory instances.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Navid Khoshavi, Hamid R. Zarandi, Mohammad Maghsoudloo	Control-flow error recovery using commodity multi-core architecture features.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Fabien Chaix, Gilles Bizot, Michael Nicolaidis, Nacer-Eddine Zergainoh	Variability-aware task mapping strategies for many-cores processor chips.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Rafal Baranowski, Hans-Joachim Wunderlich	Fail-safety in core-based system design.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Matthias Sauer, V. Tomashevich, J. Muller, Matthew D. T. Lewis, A. Spilla, Ilia Polian, Bernd Becker, W. Burgard	An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Rance Rodrigues, Sandip Kundu	On graceful degradation of microprocessors in presence of faults via resource banking.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Dhiego Silva, Leticia Maria Veiras Bolzani, Fabian Vargas	An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Ingrid Verbauwhede	The cost of cryptography: Is low budget possible?	IOLTS	2011	DBLP DOI BibTeX RDF
1	Matthias Sauer, Alejandro Czutro, Ilia Polian, Bernd Becker	Estimation of component criticality in early design steps.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Ronak Salamat, Hamid R. Zarandi	Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche	An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Marco Paolieri, Riccardo Mariani	Towards functional-safe timing-dependable real-time architectures.	IOLTS	2011	DBLP DOI BibTeX RDF