Search results for "open defects"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Resistive-open defects, Pre-charge circuits, Memory testing, Dynamic faults
3	Josh Yang, Baosheng Wang, André Ivanov	Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode.	VLSI Design	2004	DBLP DOI BibTeX RDF	6T SRAM, Area Penalty, Write Recovery, Memory testing, Test Time, Open Defects
3	Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada	Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	supply current test, time-variable electric field, test pattern generation, CMOS IC, open defects
2	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras	Experimental Characterization of CMOS Interconnect Open Defects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Full Open Defects in Nanometric CMOS.	VTS	2008	DBLP DOI BibTeX RDF	interconnect open, gate leakage current, CMOS
2	Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng	Automatic Test Pattern Generation for Interconnect Open Defects.	VTS	2008	DBLP DOI BibTeX RDF	Interconnect opens, Open-via defects, ATPG
2	Sudhakar M. Reddy, Irith Pomeranz, Chen Liu	On tests to detect via opens in digital CMOS circuits.	DAC	2008	DBLP DOI BibTeX RDF	constrained stuck-at tests, test generation, DFT, open defects
2	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.	European Test Symposium	2007	DBLP DOI BibTeX RDF
2	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.	VTS	2007	DBLP DOI BibTeX RDF
2	Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi	Diagnosis of Full Open Defects in Interconnecting Lines.	VTS	2007	DBLP DOI BibTeX RDF	Defect Diagnosis, Full Open Defect, Interconnecting Line, CMOS
2	Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl	Robust wiring networks for DfY considering timing constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	redundant wiring, timing constraint aware, open defects, design for yield
2	Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov	Fast detection of data retention faults and other SRAM cell open defects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Bram Kruseman, Manuel Heiligers	On test conditions for the detection of open defects.	DATE	2006	DBLP DOI BibTeX RDF
2	Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz	Test Generation for Open Defects in CMOS Circuits.	DFT	2006	DBLP DOI BibTeX RDF
2	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	SRAM core-cell, resistive open defects, memory testing, March test, dynamic faults
2	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
2	Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez	Resistance Characterization for Weak Open Defects.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
2	Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita	On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.	ITC	2002	DBLP DOI BibTeX RDF
2	Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada	Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field.	DELTA	2002	DBLP DOI BibTeX RDF	supply current test, time-variable electric field, test pattern generation, CMOS IC, open defects
2	Srikanth Venkataraman, Scott Brady Drummonds	A Technique for Logic Fault Diagnosis of Interconnect Open Defects.	VTS	2000	DBLP DOI BibTeX RDF	Diagnosis and Debugging, Logic Fault Diagnosis, Interconnect Open Defects, Fault Modeling and Simulation, Dynamic Diagnosis
2	Manoj Sachdev	Open Defects in CMOS RAM Address Decoders.	IEEE Design & Test of Computers	1997	DBLP DOI BibTeX RDF
1	Nor Zaidi Haron, Said Hamdioui	DfT schemes for resistive open defects in RRAMs.	DATE	2012	DBLP BibTeX RDF
1	J. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay	Impact of resistive-open defects on the heat current of TAS-MRAM architectures.	DATE	2012	DBLP BibTeX RDF
1	Daniel Arumí, Rosa Rodríguez Montanes, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Daniel Arumí, Rosa Rodríguez Montanes, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Gate Leakage Impact on Full Open Defects in Interconnect Lines.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria	Analysis of Resistive Open Defects in Drowsy SRAM Cells.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	Nachiket Rajderkar, Marco Ottavi, Salvatore Pontarelli, Jie Han, Fabrizio Lombardi	On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS.	DFT	2011	DBLP DOI BibTeX RDF
1	Ahmed Fawaz, Ameen Jaber, Ali Kassem, Ali Chehab, Ayman I. Kayssi	Assessing testing techniques for resistive-open defects in nanometer CMOS adders.	ICECS	2011	DBLP DOI BibTeX RDF
1	Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu	Modeling TSV open defects in 3D-stacked DRAM.	ITC	2010	DBLP DOI BibTeX RDF
1	Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson	Detecting and diagnosing open defects.	ITC	2010	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Diagnosis of full open defects in interconnect lines with fan-out.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Mohammad Fawaz, Nader Kobrosli, Ahmad Chkeir, Ali Chehab, Ayman I. Kayssi	Transient current and delay analysis for resistive-open defects in future 16 nm CMOS circuits.	ICECS	2010	DBLP DOI BibTeX RDF
1	Raul Chipana, Leticia Maria Veiras Bolzani, Fabian Vargas, Jorge Semião, Juan J. Rodríguez-Andina, Isabel C. Teixeira, Paulo J. Teixeira	Investigating the Use of BICS to detect resistive-open defects in SRAMs.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Jin-Tai Yan, Zhi-Wei Chen	Resource-constrained timing-driven link insertion for critical delay reduction.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	critical delay, link insertion, non-tree
1	Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Analysis of Resistive-Open Defects in SRAM Sense Amplifiers.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Yubin Zhang, Lin Huang, Feng Yuan, Qiang Xu	Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo	Small Delay Fault Model for Intra-Gate Resistive Open Defects.	VTS	2009	DBLP DOI BibTeX RDF
1	Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang	Analysis of Resistive Open Defects in a Synchronizer.	DFT	2009	DBLP DOI BibTeX RDF
1	Aymen Ladhar, Mohamed Masmoudi	A novel algorithm to extract open defects from industrial designs.	ICECS	2009	DBLP DOI BibTeX RDF
1	Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume	A Novel Approach for Improving the Quality of Open Fault Diagnosis.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Time-dependent Behaviour of Full Open Defects in Interconnect Lines.	ITC	2008	DBLP DOI BibTeX RDF
1	Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng	Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.	ITC	2008	DBLP DOI BibTeX RDF
1	Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker	A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.	European Test Symposium	2008	DBLP DOI BibTeX RDF	Small-delay defects, resistive opens, probabilistic fault coverage, bridging fault simulation
1	Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl	Considering possible opens in non-tree topology wire delay calculation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	non-tree topologies, yield, static timing analysis, delay analysis
1	Kirsi Korhonen, Outi Salo	Exploring Quality Metrics to Support Defect Management Process in a Multi-site Organization - A Case Study.	ISSRE	2008	DBLP DOI BibTeX RDF
1	Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han	Full-Chip Routing Considering Double-Via Insertion.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Wlodzimierz Jonca	Open Defects Caused by Scratches and Yield Modelling in Deep Sub-micron Integrated Circuit.	DDECS	2007	DBLP BibTeX RDF
1	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Slow write driver faults in 65nm SRAM technology: analysis and March test solution.	DATE	2007	DBLP DOI BibTeX RDF
1	Antonio Zenteno Ramirez, Guillermo Espinosa, Víctor H. Champac	Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.	DDECS	2006	DBLP BibTeX RDF
1	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor	Opens and Delay Faults in CMOS RAM Address Decoders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	address decoder delay faults, addressing methods, BIST, DFT, Memory testing, open defects
1	Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han	Novel full-chip gridless routing considering double-via insertion.	DAC	2006	DBLP DOI BibTeX RDF	redundant via insertion, routing, manufacturability
1	Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira	Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Abhishek Singh, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel	Defect Simulation Methodology for iDDT Testing.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test
1	Chien-Mo James Li, Edward J. McCluskey	Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.	DAC	2005	DBLP DOI BibTeX RDF	SRAM memories, VDSM technologies, core-cell, test, march test, dynamic faults, defect analysis
1	Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen	Memory Testing Under Different Stress Conditions: An Industrial Evaluation.	DATE	2005	DBLP DOI BibTeX RDF
1	Roberto Gómez, Alejandro Girón, Víctor H. Champac	Test of Interconnection Opens Considering Coupling Signals.	DFT	2005	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan	Data Retention Fault in SRAM Memories: Analysis and Detection Procedures.	VTS	2005	DBLP DOI BibTeX RDF
1	Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Kazuhiko Iwasaki	Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration.	IEICE Transactions	2004	DBLP BibTeX RDF
1	Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi, Takeomi Tamesada	CMOS Open Fault Detection by Appearance Time of Switching Supply Current.	DELTA	2004	DBLP DOI BibTeX RDF
1	Najwa Aaraj, Anis Nazer, Ali Chehab, Ayman I. Kayssi	Transient Current Testing of Dynamic CMOS Circuits.	DFT	2004	DBLP DOI BibTeX RDF
1	Mohamed Azimane, Ananta K. Majhi	New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders.	VTS	2004	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri	March iC-: An Improved Version of March C- for ADOFs Detection.	VTS	2004	DBLP DOI BibTeX RDF
1	Abhishek Singh, Chintan Patel, Jim Plusquellic	Fault Simulation Model for i{DDT} Testing: An Investigation.	VTS	2004	DBLP DOI BibTeX RDF
1	Rosa Rodríguez-Montañés, D. Muñoz, L. Balado, Joan Figueras	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	Analog Switch, DC defective behaviour, DC test, open defect, bridging defect
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri	Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Erik Chmelar	FPGA Interconnect Delay Fault Testing.	ITC	2003	DBLP DOI BibTeX RDF
1	Arun Krishnamachary, Jacob A. Abraham	Test generation for resistive opens in CMOS.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	resistive opens, delay testing, defect detection
1	Rosa Rodríguez-Montañés, D. Muñoz, L. Balado, Joan Figueras	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.	IOLTW	2002	DBLP DOI BibTeX RDF
1	Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura	A Persistent Diagnostic Technique for Unstable Defects.	ITC	2002	DBLP DOI BibTeX RDF
1	Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins	Parametric Failures in CMOS ICs - A Defect-Based Analysis.	ITC	2002	DBLP DOI BibTeX RDF
1	Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah	Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms.	VTS	2002	DBLP DOI BibTeX RDF
1	Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada	CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira	Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Haluk Konuk	Voltage- and current-based fault simulation for interconnect open defects.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Marcelino B. Santos, João Paulo Teixeira	Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL.	DATE	1999	DBLP DOI BibTeX RDF
1	Viera Stopjaková, Hans A. R. Manhaeve, M. Sidiropulos	On-Chip Transient Current Monitor for Testing of Low Voltage CMOS IC.	DATE	1999	DBLP DOI BibTeX RDF
1	K. Raahernifar, M. Ahmadi	On-line IDDQ fault testing for CMOS/BiCMOS logic families.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Bruce C. Kim, Krishna Marella	A Novel Test Methodology for MEMS Magnetic Micromotors.	VTS	1999	DBLP DOI BibTeX RDF
1	Víctor H. Champac, José Castillejos, Joan Figueras	IDDQ Testing of Opens in CMOS SRAMs.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	data retention faults, memory testing, opens, IDDQ
1	Kaamran Raahemifar, Majid Ahmadi	A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
1	Jian Liu, Rafic Z. Makki	Power supply current detectability of SRAM defects.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect
1	J. A. Segura, Miquel Roca, Diego Mateo, Antonio Rubio	An approach to dynamic power consumption current testing of CMOS ICs.	VTS	1995	DBLP DOI BibTeX RDF	dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current