Search results for "output buffers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Chen Lei, Zhang Zhi Quan, Wen Zhi Ping	A novel BIST approach for testing input/output buffers in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	i/o buffers, built-in self-test, fpga testing
2	Ning Dong, Jaijeet S. Roychowdhury	Automated nonlinear Macromodelling of output buffers for high-speed digital applications.	DAC	2005	DBLP DOI BibTeX RDF	I/O buffer macromodeling, nonlinear macromodeling
2	Tsern-Huei Lee, Ying-Che Kuo	Performance Evaluation of Combined Input Output Queued Switch with Finite Input and Output Buffers.	ICOIN	2002	DBLP DOI BibTeX RDF
2	Da-Chiang Chang, De-Ron Liang	Performance evaluation of Clos networks under bursty traffic.	ISPAN	1996	DBLP DOI BibTeX RDF	buffer length, performance evaluation, performance evaluation, performance, multiprocessor interconnection networks, bursty traffic, Clos networks, output buffers, submodel, cell loss probability
2	Byungho Kim, Boseob Kwon, Hyunsoo Yoon, Seungryul R. Maeng, Jung Wan Cho	Performance Analysis of Multipath Multistage Interconnection Networks with Nonuniform Output Traffic Distribution.	PDP	1996	DBLP DOI BibTeX RDF	buffer circuits, multipath multistage interconnection networks, nonuniform output traffic distribution, delay-throughput performance, packet arrival rates, output module., performance evaluation, performance analysis, delays, probability, packet switching, multistage interconnection networks, telecommunication traffic, packet delay, losses, output buffers, packet loss probability
1	Bart Feyaerts, Stijn De Vuyst, Sabine Wittevrongel, Herwig Bruneel	Session Delay in File Server Output Buffers with General Session Lengths.	ICC	2010	DBLP DOI BibTeX RDF
1	Hao-Yuan Zheng, Jia-Hui Wang, Chien-Hung Tsai, Chin-Tien Chang, Ching-Chung Lee, Chen-Yu Wang	Area-efficient R-C DACs with Low-offset Push-pull Output Buffers for a 10-bit LCD Source Driver.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Thomas Moscibroda, Onur Mutlu	A case for bufferless routing in on-chip networks.	ISCA	2009	DBLP DOI BibTeX RDF	routing, multi-core, memory systems, on-chip networks
1	Guan-Hong Jhou, Woei Lin	A Frame-Based Architecture with Shared Buffers for Slotted Optical Packet Switching.	HPCC	2009	DBLP DOI BibTeX RDF
1	Faisal Ghias Mir, Jesper Larsson Träff	Exploiting Efficient Transpacking for One-Sided Communication and MPI-IO.	PVM/MPI	2009	DBLP DOI BibTeX RDF
1	Igor S. Stievano, Ivan A. Maio, Flavio G. Canavero	Behavioral Models of IC Output Buffers From on-the-Fly Measurements.	IEEE T. Instrumentation and Measurement	2008	DBLP DOI BibTeX RDF
1	Andre Vilas Boas, Eduardo Ribeiro, Alfredo Olmos, Ricardo Maltione	Self-adaptable slew rate control output buffer for embedded microcontroller port applications.	SBCCI	2008	DBLP DOI BibTeX RDF	I/O pad, slew rate control, self-adaptable, microcontroller, output buffer
1	Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wladek Olesinski, Hans Eberle, Nils Gura	Backlog Aware Scheduling for Large Buffered Crossbar Switches.	ICC	2008	DBLP DOI BibTeX RDF
1	Petr Matas, Eva Dokladalova, Mohamed Akil, Thierry Grandpierre, L. Najman, Martin Poupa, Vjaceslav Georgiev	Parallel Algorithm for Concurrent Computation of Connected Component Tree.	ACIVS	2008	DBLP DOI BibTeX RDF
1	Alexander Scheidler, Christian Blum, Daniel Merkle, Martin Middendorf	Emergent Sorting in Networks of Router Agents.	ANTS Conference	2008	DBLP DOI BibTeX RDF
1	Yelena Rykalova, Lev B. Levitin, Richard Brower	Performance model of a multiprocessor interconnection network: theory and simulation.	SpringSim	2007	DBLP DOI BibTeX RDF	critical phenomena in networks, network saturation, latency, queueing networks, supercomputers, network performance
1	Maarten Wiggers, Marco Bekooij, Gerard J. M. Smit	Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs.	DAC	2007	DBLP DOI BibTeX RDF
1	Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang, Jyh-Herng Wang	Simultaneous block and I/O buffer floorplanning for flip-chip design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	K. Allidina, Shahriar Mirabbasi	A widely tunable active RF filter topology.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Snehashis Roy, Sukumar Jairam, H. Udayakumar	A Methodology for Switching Activity Based IO Powerpad Optimisation.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	T. Zhang, K. Lu, J. R. Jue	Shared fiber delay line buffers in asynchronous optical packet switches.	IEEE Journal on Selected Areas in Communications	2006	DBLP DOI BibTeX RDF
1	Soo-Tae Kwon	On the Optimal Buffer Allocation of an FMS with Finite In-Process Buffers.	ICCSA	2006	DBLP DOI BibTeX RDF	Throughput, Queueing Network, Buffer, FMS
1	Nilay Tanik Argon, Sigrún Andradóttir	Partial Pooling in Tandem Lines with Cooperation and Blocking.	Queueing Syst.	2006	DBLP DOI BibTeX RDF	Cross-trained servers, Cooperating servers, Work-in-process inventory, Holding costs, Throughput, Tandem queues, Finite buffers, Stochastic orders, Sample-path Analysis
1	Carlos Roberto dos Santos, Shusaburo Motoyama	A QoS Provisioned CIOQ Packet Switch Using Crossbar Structure with m Internal Links.	ICW/ICHSN/ICMCS/SENET	2005	DBLP DOI BibTeX RDF
1	Soo-Tae Kwon	On the Optimal Workloads Allocation of an FMS with Finite In-process Buffers.	ICCSA	2005	DBLP DOI BibTeX RDF	Throughput, Queueing Network, Workload, FMS
1	Johannes Sturm, Martin Leifhelm, Harald Schatzmayr, Stefan Groiss, Horst Zimmermann	Optical Receiver IC for CD/DVD/Blue-Laser Application.	DATE	2004	DBLP DOI BibTeX RDF
1	Won-Ok Kwon, Kyoung Park	Effective Digital IO Pin Modeling Methodology Based on IBIS Model.	AsiaSim	2004	DBLP DOI BibTeX RDF
1	Alexander Kesselman, Adi Rosén	Scheduling policies for CIOQ switches.	SPAA	2003	DBLP DOI BibTeX RDF	CIOQ switches, competitive analysis, buffer management, scheduling policies
1	Roberto F. Lu, Guixiu Qiao, Charles R. McLean	Manufacturing case studies: NIST XML simulation interface specification at Boeing: a case study.	Winter Simulation Conference	2003	DBLP DOI BibTeX RDF
1	Philippe Raipin Parvédy, Michel Raynal	Uniform Agreement Despite Process Omission Failures.	IPDPS	2003	DBLP DOI BibTeX RDF	Syn-chronous Distributed System, Uniform Agreement, Consensus, Crash Failure, Message Passing System, Interactive Consistency, Omission Failure
1	Jaeyoung Shin, Sunki Min, Soosun Kim, Joongho Choi, Soohyoung Lee, Hojin Park, Jaewhui Kim	3.3-V baseband Gm-C filters for wireless transceiver applications.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Valentin Puente, José A. Gregorio, Ramón Beivide, Cruz Izu	On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	hardware router design, Interconnection networks, shared memory multiprocessors, adaptive routing
1	Cyriel Minkenberg	Work-conservingness of CIOQ packet switches with limited output buffers.	IEEE Communications Letters	2002	DBLP DOI BibTeX RDF
1	Patrick Mitran, Felix Beaudoin, Mourad N. El-Gamal	A 2.5 Gbit/s CMOS optical receiver frontend.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Zhengguo Li, X. J. Yuan, Changyun Wen, Boon-Hee Soong	A switched priority scheduling mechanism for ATM switches with multi-class output buffers.	Computer Networks	2001	DBLP DOI BibTeX RDF
1	James W. Miller, Michael G. Khazhinsky, James C. Weldon	Layout and bias options for maximizing Vt1 in cascoded NMOS output buffers.	Microelectronics Reliability	2001	DBLP DOI BibTeX RDF
1	Ge Nong, Mounir Hamdi	Providing QoS Guarantees for Unicast/Multicast Traffic with Fixed/Variable-Length Packets in Multiple Input-Queued Switches.	ISCC	2001	DBLP DOI BibTeX RDF
1	Dariusz Kania	Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping.	EUROMICRO	2000	DBLP DOI BibTeX RDF
1	Dariusz Kania	Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition.	EUROMICRO	1999	DBLP DOI BibTeX RDF
1	P. Costa, Carlo Fiocchi, Umberto Gatti, Franco Maloberti	High-performance BiCMOS output buffer design strategies.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Sang Won Song, M. Ismail, Gyu Moon, Dong Yong Kim	Accurate modeling of simultaneous switching noise in low voltage digital VLSI.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Eiji Oki, Naoaki Yamanaka	Tandem-crosspoint ATM switch with input and output buffers.	IEEE Communications Letters	1998	DBLP DOI BibTeX RDF
1	Zsehong Tsai, Ta-Chun Lo	Performance of a Multicast ATM Switch with Finite Input and Output Buffers.	J. Inf. Sci. Eng.	1997	DBLP BibTeX RDF
1	Manfred Liebhart	Performance Aspects of Switched SCI Systems. (PDF / PS)	HPDC	1997	DBLP DOI BibTeX RDF
1	Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer	Analysis of Ground Bounce in Deep Sub-Micron Circuits.	VTS	1997	DBLP DOI BibTeX RDF	deep sub-micron technology, ground bounce
1	S. R. Vemuru	Effects of simultaneous switching noise on the tapered buffer design.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
1	Derek C. W. Pao, W. N. Chau	Design of ATM switch using hypercube with distributed shared input buffers and dedicated output buffers.	ICNP	1995	DBLP DOI BibTeX RDF
1	Chan Jung Youn, Chong Kwan Un	Performance Analysis of Packet Switches with Input and Output Buffers.	Computer Networks and ISDN Systems	1994	DBLP DOI BibTeX RDF
1	Tsern-Huei Lee, Shun-Jee Liu	Performance Analysis of a Large-Scale ATM Switch with Input and Output Buffers.	INFOCOM	1994	DBLP BibTeX RDF
1	Hideaki Yamashita	Discrete-time analysis of a classified multi-server queue with burst arrivals and a shared buffer.	Queueing Syst.	1994	DBLP DOI BibTeX RDF	burst arrival, Markov chain, ATM switch, Discrete-time queue, shared buffer
1	Anil K. Gupta, Nicolas D. Georganas	Analysis of a Packet Switch with Input and Output Buffers and Speed Constraints.	INFOCOM	1991	DBLP BibTeX RDF
1	Bernd J. Krämer	Specifying concurrent objects.	SIGPLAN Notices	1989	DBLP DOI BibTeX RDF
1	K. K. Bagchi, Pradip K. Das, B. B. Bhaumik	An approach to parallel architecture modelling (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
1	Robert C. Gammill	GPMX: a portable general purpose macro processor adapted for preprocessing FORTRAN.	AFIPS National Computer Conference	1976	DBLP DOI BibTeX RDF