Search results for "parallel architecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Shih-Ching Ou, Li-Hong Shiu, Sung-Jung Hsiao, Wen-Tsai Sung	Accelerate the Calculation of NURBS curves and surfaces Based on Parallel Architecture.	ICPADS	2002	DBLP DOI BibTeX RDF	FPGA, parallel architecture, NURBS, OpenGL
3	Wael M. Badawy, Magdy A. Bayoumi	A Multiplication-Free Parallel Architecture for Affine Transformation.	ASAP	2000	DBLP DOI BibTeX RDF	parallel architecture, Video, mesh, VLSI architecture, affine transformation, triangular patches
3	Shinhaeng Lee, Hirotomo Aso	A Parallel Architecture for High Speed Fractal Image Coding.	ISPAN	1999	DBLP DOI BibTeX RDF	fractal image coding, parallel architecture, systolic array, VLSI architecture
3	Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger	A Partitioning Programming Environment for a Novel Parallel Architecture. (PDF / PS)	IPPS	1996	DBLP DOI BibTeX RDF	partitioning programming environment, novel parallel architecture, embedded accelerator, reconfigurable datapath hardware, accelerator partitioning, profiling-driven partitioning, resource-driven sequential partitioning, resource-driven structural partitioning, parallel architectures, software tools, programming environments, reconfigurable architectures, software performance evaluation, parallelizing compiler, performance optimization, program interpreters, parallelising compilers, parallelizing programming environment, optimising compilers, C programs
3	Wen-Yu Tseng, Chin-Chou Chen, David S. L. Wei, Sy-Yen Kuo	Design and Implementation of a High Speed Parallel Architecture for ATM UNI.	ISPAN	1996	DBLP DOI BibTeX RDF	UNI, VLSI, Parallel architecture, ATM
3	Francisco Argüello, Javier D. Bruguera, Ramon Doallo, Emilio L. Zapata	Parallel Architecture for Fast Transforms with Trigonometric Kernel.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	fasttransforms, trigonometric kernel, fast orthogonal transforms, Complex Valued FourierTransform, Real Valued Fourier Transform, Hartley Transform, successive doubling method, constant geometry flow, perfect unshuffle, hardware modification, circular CORDIC rotator, data recirculations, partitioned parallelarchitecture, cycle loss, systolic computation, parallel algorithms, parallel architectures, parallel architecture, transforms, systolic array, Fourier transforms, mathematics computing, shuffle, butterflies, multiprocessor interconnectionnetworks, Cosine Transform
3	Maurice Milgram, Thierry de Saint Pierre	Boundary Detection and Skeletonization with a Massively Parallel Architecture.	IEEE Trans. Pattern Anal. Mach. Intell.	1990	DBLP DOI BibTeX RDF	TOSCA, edge pixel detection, token propagation, counting devices, local processing, parallel architectures, computerised pattern recognition, computerised pattern recognition, skeletonization, cellular automaton, boundary detection, massively parallel architecture, Chamfer distance
2	Gang Liu	An Image Retrieval System Based on Parallel Architecture.	WKDD	2010	DBLP DOI BibTeX RDF	Feature Extraction, Parallel Architecture, Image Retrieval
2	Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel	High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Block turbo decoding, Full-parallel architecture, Complexity analysis, FPGA implementation
2	Gerd Pfeiffer, Stefan Baumgart, Jan Schröder, Manfred Schimmler	A Massively Parallel Architecture for Bioinformatics.	ICCS	2009	DBLP DOI BibTeX RDF
2	Mihaela Malita, Gheorghe Stefan	Integral Parallel Architecture & Berkeley's Motifs.	ASAP	2009	DBLP DOI BibTeX RDF
2	Weirong Jiang, Viktor K. Prasanna	A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification.	ASAP	2009	DBLP DOI BibTeX RDF
2	Oguzhan Erdem, Cüneyt F. Bazlamaçci	MIPS extension for a TCAM based parallel architecture for fast IP lookup.	ISCIS	2009	DBLP DOI BibTeX RDF
2	Javier Navaridas, Mikel Luján, José Miguel-Alonso, Luis A. Plana, Steve Furber	Understanding the interconnection network of SpiNNaker.	ICS	2009	DBLP DOI BibTeX RDF	biologically inspired architecture, performance evaluation, fault tolerance, interconnection networks, systems on chip, real-time applications, spiking neurons, massively parallel architecture, analytical evaluation
2	Amin Ansari, Keyvan Amiri	Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains.	FPGA	2008	DBLP DOI BibTeX RDF	deinterleaver, pulse train, FPGA, parallel architecture
2	Kota Naga Srinivasarao Batta, Indrajit Chakrabarti	A Parallel Architecture for Successive Elimination Block Matching Algorithm.	ICVGIP	2008	DBLP DOI BibTeX RDF
2	Hiroshige Hayashizaki, Yutaka Sugawara, Mary Inaba, Kei Hiraki	MCAMP: communication optimization on massively parallel machines with hierarchical scratch-pad memory.	PACT	2008	DBLP DOI BibTeX RDF	GRAPE-DR, copy candidates, scratch-pad memory management, memory hierarchy, massively parallel architecture
2	Ronald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David Blaauw, Dennis Sylvester	An Energy Efficient Parallel Architecture Using Near Threshold Operation.	PACT	2007	DBLP DOI BibTeX RDF
2	Jian Huang, Hao Li	A Parallel Architecture for Motion Estimation and DCT Computation in MPEG-2 Encoder.	ICA3PP	2007	DBLP DOI BibTeX RDF
2	Rachit Agarwal, Emanuel M. Popovici, Brendan O'Flynn, Michael E. O'Sullivan	A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Edson Pedro Ferlin, Heitor S. Lopes, Carlos R. Erig Lima, Ederson Cichaczewski	Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits.	ARC	2007	DBLP DOI BibTeX RDF
2	Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin	A Parallel Architecture for Hardware Face Detection.	ISVLSI	2006	DBLP DOI BibTeX RDF
2	Li Bao-Feng, Shao Qiang	Deeply Parallel Architecture for Lifting-Based 2D DWT in JPEG2000.	CIT	2006	DBLP DOI BibTeX RDF
2	Wei-Kai Chan, Shao-Yi Chien	Subword Parallel Architecture for Connected Component Labeling and Morphological Operations.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Ph. Philipov, Vladimir Lazarov, Z. Zlatev, M. Ivanova	A Parallel Architecture for Radix-2 Fast Fourier Transform.	John Vincent Atanasoff Symposium	2006	DBLP DOI BibTeX RDF	Highperformance computer architectures, Parallel Fast Fourier Transform
2	Yizhen Zhang, Chao Xu	Analysis and high performance parallel architecture design for EBCOT in JPEG2000.	ICIP	2005	DBLP DOI BibTeX RDF
2	Yanju Han, Chao Xu, Yizhen Zhang	An improved bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	In-Cheol Park, Se-Hyeon Kang	Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Maria J. Avedillo, José M. Quintana, Hamid El Alami, Antonio Jiménez-Calderón	A Practical Parallel Architecture for Stacks Filters.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	stack filters, threshold decomposition, threshold logic, non-linear filters
2	Viorela Ila, Rafael García, François Charot	Proposal of a Parallel Architecture for a Motion Detection Algorithm.	ICPR	2004	DBLP DOI BibTeX RDF
2	Eric J. Swankoski, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	A Parallel Architecture for Secure FPGA Symmetric Encryption.	IPDPS	2004	DBLP DOI BibTeX RDF
2	Nazar A. Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-Pérez	A Parallel Architecture for Fast Computation of Elliptic Curve Scalar Multiplication over GF(2^m).	IPDPS	2004	DBLP DOI BibTeX RDF
2	Nazar A. Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-Pérez	A Parallel Architecture for Computing Scalar Multiplication on Hessian Elliptic Curves.	ITCC	2004	DBLP DOI BibTeX RDF
2	Marjan Karkooti, Joseph R. Cavallaro	Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding.	ITCC	2004	DBLP DOI BibTeX RDF	FPGA imple-mentation, area-time tradeoffs, parallel architecture, Reconfigurable architecture, channel coding
2	Diogo Zandonai, Sergio Bampi, Marcel Bergerman	ME64 - A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGA.	SBCCI	2003	DBLP DOI BibTeX RDF
2	An-Te Deng, Winser E. Alexander	Dual clock rate block data parallel architecture.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Harald Simmler, Holger Singpiel, Reinhard Männer	Real-Time Primer Design for DNA Chips.	IPDPS	2003	DBLP DOI BibTeX RDF	Primer design, High performance parallel architecture, FPGA, Hardware accelerator, HPC
2	Wael M. Badawy, Magdy Bayoumi	A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation.	VLSI Signal Processing	2002	DBLP DOI BibTeX RDF	VLSI, low power, texture mapping, MPEG-4, affine transformation, video object
2	Kyo-Min Ku, Kyeoung Ju Ha, Hyun-Sung Kim, Kee-Young Yoo	New Parallel Architecture for Modular Multiplication and Squaring Based on Cellular Automata.	PARA	2002	DBLP BibTeX RDF
2	Leo Chin Sim, Heiko Schröder	Fast Processing of Medical Images Using a New Parallel Architecture, the Hybrid System. (PDF / PS)	SSIAI	2002	DBLP DOI BibTeX RDF	Parallelization, Volume Rendering, Hybrid System, SIMD, Speedup, MIMD
2	José Fridman, Elias S. Manolakos	Distributed Memory Parallel Architecture Based on Modular Linear Arrays for 2-D Separable Transforms Computation.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	2-D separable transforms, parallel processing, VLSI architectures
2	Bertil Schmidt, Heiko Schröder, Manfred Schimmler	Scanning Biosequence Databases on a Hybrid Parallel Architecture.	Euro-Par	2001	DBLP DOI BibTeX RDF
2	Ghazi Al-Rawi, John M. Cioffi	A Highly Efficient Domain-Programmable Parallel Architecture for Iterative LDPCC Decoding.	ITCC	2001	DBLP DOI BibTeX RDF
2	Juliette Mattioli, Nicolas Museux, Jean Jourdan, Pierre Savéant, Simon de Givry	A Constraint Optimization Framework for Mapping a Digital Signal Processing Application onto a Parallel Architecture.	CP	2001	DBLP DOI BibTeX RDF
2	Lucas Szajek, Lev Kirischian	Implementation of an Adaptive Reconfigurable Group Organized (ARGO) Parallel Architecture.	PARELEC	2000	DBLP DOI BibTeX RDF
2	Hon Nin Cheung, Li-minn Ang, Kamran Eshraghian	Parallel Architecture for the Implementation of the Embedded Zerotree Wavelet Algorithm.	ACAC	2000	DBLP DOI BibTeX RDF	EZW, Parallel processing, image coding
2	Shinhaeng Lee, Shinichiro Omachi, Hirotomo Aso	A Parallel Architecture for Quadtree-based Fractal Image Coding. (PDF / PS)	ICPP	2000	DBLP DOI BibTeX RDF
2	Paula N. Mallón, Montserrat Bóo, Javier D. Bruguera	Parallel Architecture for Conversion of NURBS Curves to Bézier Curves.	EUROMICRO	2000	DBLP DOI BibTeX RDF
2	Babu Mailachalam, T. Srikanthan	A Robust Parallel Architecture for Adaptive Color Quantization.	ITCC	2000	DBLP DOI BibTeX RDF
2	Milton Romero, Bruno Ciciani	A Parallel Architecture for Stereoscopic Processing.	Euro-Par	1999	DBLP DOI BibTeX RDF
2	Bojana Obrenic, Martin C. Herbordt, Arnold L. Rosenberg, Charles C. Weems	Using Emulations to Enhance the Performance of Parallel Architectures.	IEEE Trans. Parallel Distrib. Syst.	1999	DBLP DOI BibTeX RDF	parallel algorithms, Parallel architecture, multiprocessor interconnection
2	Harvey Ray, Hanspeter Pfister, Deborah Silver, Todd A. Cook	Ray Casting Architectures for Volume Visualization.	IEEE Trans. Vis. Comput. Graph.	1999	DBLP DOI BibTeX RDF	VOGUE, VIRIM, array based ray casting, EM-Cube, VIZARD II, interactive, parallel architecture, Volume rendering, ray casting
2	Andrew M. Wallace, Greg Michaelson, Norman Scaife, W. J. Austin	A Dual Source, Parallel Architecture for Computer Vision.	The Journal of Supercomputing	1998	DBLP DOI BibTeX RDF	parallel vision, multi-source data, cooperative processing
2	Chouki Aktouf, Chantal Robach, A. Marinescu, Guy Mazaré	An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	routing test, IEEE 1149.1, built-in self-test, diagnosis, MIMD architectures
2	Giuseppe Ascia, Vincenzo Catania	A Framework for a Parallel Architecture Dedicated to Soft Computing.	VLSI Design	1998	DBLP DOI BibTeX RDF	VLSI, Parallel Architecture, Soft Computing
2	Dominique Houzet, Abdelkrim Fatni	Pc-based Shared Memory Architecture and Language.	The Journal of Supercomputing	1998	DBLP DOI BibTeX RDF	Evaluation, Image Processing, Parallel Architecture, Language
2	Kiyoharu Aizawa, Takayuki Hamamoto, Yasuhiro Ohtsuka, Mitsutoshi Hatori, M. Abe	Implementations of on Sensor Image Compression and Comparisons Between Pixel and Column Parallel Architectures. (PDF / PS)	ICIP	1997	DBLP DOI BibTeX RDF	sensor image compression, column parallel architecture, image signal, high pixel rate sensing, conditional replenishment, moving areas encoding, pixel parallel architecture, performance, image coding
2	Sook-Yeon Kim, Kyung-Yong Chwa	Optimal embeddings of multiple graphs into a hypermesh. (PDF / PS)	ICPADS	1997	DBLP DOI BibTeX RDF	optimal embeddings, multiple graphs, hypermesh, versatile parallel architecture, 2-dimensional mesh, linear connection, hyper-edge, labeling strategy, optimal expansion, N-node graph, hypercube, hypercube networks, congestion, torus, dilation
2	Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi	CODA-R: a reconfigurable testbed for real-time parallel computation.	RTCSA	1997	DBLP DOI BibTeX RDF	CODA-R, reconfigurable testbed, real-time parallel computation, reconfigurable field programmable gate arrays, total execution time, prototype reconfigurable real-time parallel system, real-time parallel architecture, field programmable gate arrays, real-time system, processing elements, computing engine
2	Wen-jann Yang, Ramalingam Sridhar, Victor Demjanenko	Parallel Intersecting Compressed Bit Vectors in a High Speed Query Server for Processing Postal Addresses.	HPCA	1996	DBLP DOI BibTeX RDF	List intersection hardware, Parallel architecture, Compression, Inverted file
2	R. S. Hogg, W. I. Hughes, David W. Lloyd	A Novel Asynchronous ALU for Massively Parallel Architectures.	PDP	1996	DBLP DOI BibTeX RDF	novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit
2	Juan C. Moure, Daniel Franco 0002, Elisa Heymann, Emilio Luque	TransCom: A Communication Microkernel for Transputers.	PDP	1996	DBLP DOI BibTeX RDF	communication microkernel, TransCom, TransRouter, data transport, processor resource, parallel programming, parallel programming, parallel architecture, message passing, message passing, communication network, communication protocols, distributed memory systems, processor scheduling, network operating systems, access protocols, operating system kernels, transputers, distributed-memory multiprocessor, load distribution, communication primitives, transputer systems
2	Franco Zambonelli, Matteo Pugassi, Letizia Leonardi, Nello Scarabottolo	Experiences on Porting a Parallel Objects Environment from a Transputer Network to a PVM-Based System.	PDP	1996	DBLP DOI BibTeX RDF	Parallel Objects, parallel object-oriented programming, PVM environment, heterogeneous computer networks, parallel programming, object-oriented programming, programming environments, computer aided software engineering, software portability, massively parallel architecture
2	M. P. Sebastian, P. S. Nagendra Rao, Lawrence Jenkins	VLSI/WSI Designs for Folded Cube-Connected Cycles Architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF	Building block design, fault-tolerance, reliability, parallel architecture, layout, yield
2	Vijay Singh Riyait, Michael Andrew Lawlor, Alan E. Adams, Oliver R. Hinton, Bayan S. Sharif	Real-time synthetic aperture sonar imaging using a parallel architecture.	IEEE Transactions on Image Processing	1995	DBLP DOI BibTeX RDF
2	Francesco Gregoretti, Claudio Passerone	Using a massively parallel architecture for integrated circuits testing.	PDP	1995	DBLP DOI BibTeX RDF	VLSI integrated circuit, low level image processing, image processing, parallel architectures, prototype, integrated circuit testing, integrated circuits testing, Integrated Circuits, massively parallel architecture, Scanning Electron Microscopy
2	Ut-Va Koc, K. J. Ray Liu	Adaptive overlapping approach for DCT-based motion estimation. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	DCT based motion estimation, adaptive overlapping approach, temporal prediction, MPEG compliant video coder, image conversion, coder throughput, uniformly bright environment, parallel architectures, parallel architecture, stability, motion estimation, video coding, discrete cosine transforms, simulation results, transform coding, stability analysis, adaptive signal processing, telecommunication standards, prediction theory, feedback loop, code standards, spatial domain, transform domain, video coding standards
2	Sheng-Yih Guan, Avi Bleiweiss, Richard Lipes	Parallel implementation of volume rendering on Denali graphics systems. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	computer graphic equipment, computer peripheral equipment, Denali graphics systems, 3D graphics systems, texture mapping capability, standard graphics pipeline, pipelined parallel architecture, Kubota Graphics Corporation, maximum intensity projection, iso-surface rendering, partitioning data allocation scheme, texture memory requirements, transformation and rasterization modules, frame buffer modules, parallel node, general purpose RISC processor, object parallelism, hardware ASICs, pixel memory, pixel parallelism, resource allocation, parallel architectures, volume rendering, pipeline processing, dynamic load balancing, image texture, parallel implementation, rendering (computer graphics), reduced instruction set computing, static load balancing
2	Oguz Dikenelli, Murat Osman Ünalir, Atilla Özerdim, Esen A. Ozkarahan	A load balancing approach for parallel database machines.	PDP	1995	DBLP DOI BibTeX RDF	parallel database machines, multiattribute declustering, load balancing, resource allocation, parallel architecture, distributed databases, database machines, database machines, parallel database systems
2	Ronald F. DeMara, Dan I. Moldovan	The SNAP-1 Parallel AI Prototype.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	SNAP-1 parallel AI prototype, Semantic Network Array Processor, marker-propagation paradigm, natural languageunderstanding, multiprocessing clusters, dedicated communication units, tiered synchronization scheme, multiported memorynetwork, speech analysis andprocessing, knowledge representation, parallel architecture, parallel architectures, natural languages, reasoning, inference mechanisms, semantic networks, speech processing, digital signal processors, special purpose computers, parallelmachines
2	Dominique Houzet, Jean-Luc Basille, Jean-Yves Latil	Performance Analysis of the Network of the GFLOPS Parallel Architecture.	PARLE	1992	DBLP DOI BibTeX RDF
2	V. David, C. Fraboul, J. Y. Rousselot, Pierre Siron	Partitioning and Mapping Communication Graphs on a Modular Reconfigurable Parallel Architecture.	CONPAR	1992	DBLP DOI BibTeX RDF
2	Bernd Schütz, Reinhard Rauscher	A Parallel Architecture for a VLSI-Hardware-Realization.	CONPAR	1992	DBLP DOI BibTeX RDF
2	Jerry Stach, Jerry Place	A Performance Study of a Highly-Parallel Architecture to Provide Registration and Translation Services in an Intelligent Network.	ACM Conference on Computer Science	1992	DBLP DOI BibTeX RDF
2	Dan I. Moldovan, Wing Lee, Changhwa Lin	SNAP: A Market-Propagation Architecture for Knowledge Processing.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	knowledge storage, market-propagation architecture, semantic network array processor, artificialintelligence, custom-designedchips, reasoning mechanisms, marker propagation rules, 16 kB, knowledge representation, knowledge representation, parallel architecture, knowledge based systems, natural languages, knowledge base, natural language understanding, printed circuit boards, knowledge processing, SNAP, parallelarchitectures
2	Emilio L. Zapata, Francisco Argüello	A VLSI Constant Geometry Architecture for the Fast Hartley and Fourier Transforms.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	fast Hartley transform, VLSI constant geometryarchitecture, parallel calculation, constant geometry algorithm, perfect unshuffle permutation, processormemory, systolic data flow, multiplexing operations, hardwired control, parallel algorithms, VLSI, parallel architecture, parallel architectures, fast Fourier transform, fast Fourier transforms, butterflies, FIFO queues, application-specific architecture, computationalcomplexity
2	Minghua Chen, Theodosios Pavlidis	Image Seaming for Segmentation on Parallel Architecture.	IEEE Trans. Pattern Anal. Mach. Intell.	1990	DBLP DOI BibTeX RDF	image tiles, seaming algorithm, gray-level mean difference, maximum-minimum criteria, Sequent machine, Sun 3/160 workstation, segmentation, parallel architecture, parallel architectures, computerised picture processing, computerised picture processing, image analysis, minimax techniques
2	Ahmed Louri	A Symbolic Substitution Based Parallel Architecture and Algorithms for High-speed Parallel Processing.	ACM Conference on Computer Science	1990	DBLP DOI BibTeX RDF
2	Louis O. Hertzberger, Willem G. Vree	A Coarse Grain Parallel Architecture for Functional Languages.	PARLE	1989	DBLP DOI BibTeX RDF
1	Daniele Bernabei, Ajit Hakke Patil, Francesco Banterle, Marco Di Benedetto, Fabio Ganovelli, Sumanta N. Pattanaik, Roberto Scopigno	A Parallel Architecture for Interactively Rendering Scattering and Refraction Effects.	IEEE Computer Graphics and Applications	2012	DBLP DOI BibTeX RDF
1	Francisco Barranco, Matteo Tomasi, Javier Díaz, Mauricio Vanegas, Eduardo Ros	Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Santonu Sarkar, Mageri Filali Maltouf	Identifying hotspots in a program for data parallel architecture: an early experience.	ISEC	2012	DBLP DOI BibTeX RDF
1	Huailu Ren, Yibo Fan, Xinhua Chen, Xiaoyang Zeng	A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	L. H. Han, T. Indinger, X. Y. Hu, N. A. Adams	Wavelet-based adaptive multi-resolution solver on heterogeneous parallel architecture for computational fluid dynamics.	Computer Science - R&D	2011	DBLP DOI BibTeX RDF
1	Edson Pedro Ferlin, Heitor Silvério Lopes, Carlos R. Erig Lima, Mauricio Perretto	A FPGA-Based Reconfigurable Parallel Architecture for High-Performance Numerical Computation.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF
1	Yong Ding, Xiaolang Yan	A robust motion estimation with center-biased diamond search and its parallel architecture for motion-compensated de-interlace.	The Journal of Supercomputing	2011	DBLP DOI BibTeX RDF
1	Jason Sewall, Jatin Chhugani, Changkyu Kim, Nadathur Satish, Pradeep Dubey	PALM: Parallel Architecture-Friendly Latch-Free Modifications to B+ Trees on Many-Core Processors.	PVLDB	2011	DBLP BibTeX RDF
1	David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq Kuen Lee, Yuan-Hua Chu, An-Yeu Wu	Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools.	Signal Processing Systems	2011	DBLP DOI BibTeX RDF
1	Jia-Ming Chen, Chun-Nan Liu, Jen-Kuei Yang, Shau-Yin Tseng, Wei Kuan Shih, An-Yeu Wu	Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part II: Application Programming.	Signal Processing Systems	2011	DBLP DOI BibTeX RDF
1	Dong-Rui Fan, Xiao-Wei Li, Guo-Jie Li	New Methodologies for Parallel Architecture.	J. Comput. Sci. Technol.	2011	DBLP DOI BibTeX RDF
1	Kishor Sarawadekar, Swapna Banerjee	An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000.	IEEE Trans. Circuits Syst. Video Techn.	2011	DBLP DOI BibTeX RDF
1	Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee	A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Madusudanan Sathia Narayanan, Srikanth Kannan, Xiaobo Zhou, Frank Mendel, Venkat Krovi	Parallel Architecture Manipulators for Use in Masticatory Studies.	IJIMR	2011	DBLP DOI BibTeX RDF
1	Edson Pedro Ferlin, Heitor S. Lopes, Carlos R. Erig Lima, Mauricio Perretto	PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model.	IJHPSA	2011	DBLP DOI BibTeX RDF
1	Xinyu Guo, Hong Wang, Vijay Devabhaktuni	Design of a FPGA-Based Parallel Architecture for BLAST Algorithm with Multi-hits Detection.	ITNG	2011	DBLP DOI BibTeX RDF
1	Andrea Caponio, Mauricio Hincapié, Eduardo González Mendívil	lMAR: Highly Parallel Architecture for Markerless Augmented Reality in Aircraft Maintenance.	HCI	2011	DBLP DOI BibTeX RDF
1	David Ródenas, Francesc Serratosa, Albert Solé-Ribalta	Graph Matching on a Low-Cost and Parallel Architecture.	IbPRIA	2011	DBLP DOI BibTeX RDF
1	Edgar J. Garcia Neto Segundo, Nadia Nedjah, Luiza de Macedo Mourelle	A Parallel Architecture for DNA Matching.	ICA3PP	2011	DBLP DOI BibTeX RDF
1	Christine Rochange	An Overview of Approaches Towards the Timing Analysability of Parallel Architecture.	PPES	2011	DBLP DOI BibTeX RDF
1	Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak	A parallel architecture for ray-tracing with an embedded intersection algorithm.	ISCAS	2011	DBLP DOI BibTeX RDF