Search results for "parallel architectures"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary	Compiler Algorithms for Optimizing Locality and Parallelism on Shared and Distributed Memory Machines.	IEEE PACT	1997	DBLP DOI BibTeX RDF	storage layout, SUN SPARCstation 5, IBM SP-2, SGI Challenge, Convex Exemplar, parallel architectures, parallel architectures, optimizing compilers, interprocessor communication, cache performance, distributed memory machines, shared memory machines, loop nests, data decomposition, compiler algorithms
4	Hussein M. Alnuweiri, Viktor K. Prasanna	Parallel Architectures and Algorithms for Image Component Labeling.	IEEE Trans. Pattern Anal. Mach. Intell.	1992	DBLP DOI BibTeX RDF	image component labeling, computer vision, computer vision, parallel algorithms, parallel algorithms, parallel architectures, parallel architectures, image recognition
3	Erik R. Altman, James C. Dehnert, Christoph W. Kessler, Jens Knoop	05101 Abstracts Collection - Scheduling for Parallel Architectures: Theory, Applications, Challenges.	Scheduling for Parallel Architectures	2005	DBLP BibTeX RDF
3	Erik R. Altman, James C. Dehnert, Christoph W. Kessler, Jens Knoop	05101 Executive Summary - Scheduling for Parallel Architectures: Theory, Applications, Challenges.	Scheduling for Parallel Architectures	2005	DBLP BibTeX RDF
3	Yen-Kuang Chen, S. Y. Kung	An Operation Placement and Scheduling Scheme for Cache and Communication Localities in Fine-Grain Parallel Architectures.	ISPAN	1997	DBLP DOI BibTeX RDF	operation placement and scheduling, performance optimization of instruction-level parallelism, VLSI array processor design methodology, multi-dimensional projection, multiprojection, Parallel compiler
3	Yingchun Zhu, Laurie J. Hendren	Locality Analysis for Parallel C Programs.	IEEE PACT	1997	DBLP DOI BibTeX RDF	parallel C programs, parallel C dialect, EARTH-C, type inference algorithms, fast points-to analysis, indirect reference, automatic specialization, EARTH-C compiler, low level threaded code, EARTH-C multithreaded architecture, dynamically allocated data structures, parallel programming, parallel architectures, memory model, compiler techniques, parallel performance, locality analysis, remote memory accesses
3	Jing-Chiou Liou, Michael A. Palis	CASS: an efficient task management system for distributed memory architectures.	ISPAN	1997	DBLP DOI BibTeX RDF	CASS, granularity optimization, parallel algorithm, parallelism, compiler, parallel architectures, operating system, task scheduling, task management, distributed memory architectures
3	Richard D. Dietz, Thomas L. Casavant, Todd E. Scheetz, Terry A. Braun, Mark S. Andersland	Modeling the impact of run-time uncertainty on optimal computation scheduling using feedback. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	run-time uncertainty, computation scheduling, run-time variance, static-dynamic scheduling, SEDIA, monitoring intrusion, parallel architectures, parallel architectures, feedback
3	Jürgen Brehm, Patrick H. Worley	Performance Prediction for Complex Parallel Applications. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	complex parallel applications, massively parallel machines, parallel design decisions, parallelization strategies, Performance Prediction Tool, PerPreT, Parallel Spectral Transform Shallow Water Model code, parallel architectures, parallel architectures, performance prediction, message-passing systems, Intel Paragon
3	R. S. Hogg, W. I. Hughes, David W. Lloyd	A Novel Asynchronous ALU for Massively Parallel Architectures.	PDP	1996	DBLP DOI BibTeX RDF	novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit
3	Chi-Hsiang Yeh, Behrooz Parhami	Swapped networks: unifying the architectures and algorithms of a wide class of hierarchical parallel processors. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	swapped networks, hierarchical parallel processors, high-dimensional meshes, generalized hypercubes, fixed-degree building blocks, parallel algorithms, interconnection networks, parallel architectures, parallel architectures, hypercubes, multiprocessor interconnection networks
3	John Lloyd	Parallel Formulations of Matrix-Vector Multiplication for Matrices with Large Aspect Ratios.	PDP	1996	DBLP DOI BibTeX RDF	parallel formulations, large aspect ratio matrices, square matrices, square meshes, wraparound connections, parallel algorithms, parallel algorithms, parallel architectures, parallel architectures, partitioning, hypercubes, hypercube networks, matrix multiplication, communication overhead, matrix-vector multiplication
3	Phyllis Crandall, Michael J. Quinn	Non-uniform 2-D grid partitioning for heterogeneous parallel architectures. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	nonuniform 2D grid partitioning, heterogeneous parallel architectures, uniform computational requirements, block decomposition method, Fair Binary Recursive Decomposition, performance level, performance evaluation, parallel architectures, decomposition technique
3	Yung-Kang Chu, I-Ling Yen, Diane T. Rover	Guiding processor allocation with estimated execution time for mesh connected multiple processor systems. (PDF / PS)	HICSS	1995	DBLP DOI BibTeX RDF	estimated execution time, mesh connected multiple processor systems, mesh connected parallel architectures, multiprocessor systems design, submesh allocation strategies, two-dimensional mesh systems, estimated execution times, submesh allocation, processor allocation strategies, extensive simulations, system performance improvement, execution failures, scheduling, performance, resource allocation, parallel architectures, response time, processor scheduling, software performance evaluation, execution time, processor allocation, standard deviation, job characteristics, load conditions
3	Steven Parkes, Prithviraj Banerjee, Janak H. Patel	A parallel algorithm for fault simulation based on PROOFS . (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning
3	Afonso Ferreira, Stéphane Ubéda	Parallel complexity of the medial axis computation. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	medial axis computation, block-based digital medial axis transform, parallel prefix operations, work-optimal parallel algorithms, time-optimal parallel algorithms, image oversampling, parallel algorithms, computational complexity, parallel architectures, parallel architectures, binary image, image sampling, parallel complexity, image labelings, scan operations
3	Kim S. Larsen, Rolf Fagerberg	B-trees with relaxed balance. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	relaxed balance, shared-memory asynchronous parallel architectures, rebalancing, extensive locking, maximal size, parallel architectures, B-trees, tree data structures, subtree
3	K. J. Runge, L. P. Lee, J. Correa, R. T. Scalettar, Vojin G. Oklobdzija	Monte Carlo and molecular dynamics simulations using p4. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	p4, interacting electrons, mobile electrons, parallel programming system, MD simulation, MC simulation, interacting phonons, parallel algorithms, parallel architectures, parallel architectures, digital simulation, Monte Carlo methods, Monte Carlo simulations, software libraries, physics computing, mathematics computing, molecular dynamics simulations, solid, molecular dynamics method
3	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva	A portable ATPG tool for parallel and distributed systems.	VTS	1995	DBLP DOI BibTeX RDF	portable ATPG tool, memory critical problems, electronic CAD, code portability, PVM library, DEC Alpha AXP, genetic algorithms, genetic algorithm, distributed systems, parallel architectures, parallel architectures, logic testing, message passing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, logic CAD, parallel systems, software portability, message-passing libraries, CM-5
3	Alok N. Choudhary, Bhagirath Narahari, David M. Nicol, Rahul Simha	Optimal Processor Assignment for a Class of Pipelined Computations.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	multitasked parallel architectures, processor assignment problem, series-parallel partial order, parallel analysis, task structure, series-parallel task system, series analysis, computer vision, resource allocation, parallel architectures, data dependencies, pipeline processing, data sets, pipelined computations
3	Kemal Efe	The Crossed Cube Architecture for Parallel Computation.	IEEE Trans. Parallel Distrib. Syst.	1992	DBLP DOI BibTeX RDF	self routing network, crossed cube architecture, distributed routingalgorithm, high connectivity, SIMD algorithms, CQ/sub n/ architecture, dynamicreconfiguration, embedding properties, parallel algorithms, parallel computation, parallel architectures, regularity, symmetry, switches, multiprocessorinterconnection networks, massively parallel architectures, hypercube algorithms, recursive structure
3	Mark A. Yoder, Leah H. Jamieson	Simulation of a Word Recognition System on Two Parallel Architectures.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	word recognition system, VLSI processor array, 8-MHz MC68000, 12-MHz Intel 8051, simulations, parallel algorithms, parallel algorithms, parallel architectures, parallel architectures, speech recognition, SIMD, digital simulation
2	Byunghyun Jang, Dana Schaa, Perhaad Mistry, David R. Kaeli	Exploiting Memory Access Patterns to Improve Memory Performance in Data-Parallel Architectures.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	General-purpose computation on GPUs (GPGPUs), memory access pattern, memory selection, memory coalescing, data-parallel architectures, vectorization, data parallelism, memory optimization, GPU computing
2	Byunghyun Jang, Perhaad Mistry, Dana Schaa, Rodrigo Dominguez, David R. Kaeli	Data transformations enabling loop vectorization on multithreaded data parallel architectures.	PPOPP	2010	DBLP DOI BibTeX RDF	loop vectorization, gpgpu, data transformation
2	Min Li, David Novo, Bruno Bougard, Trevor Carlson, Liesbet Van der Perre, Francky Catthoor	Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures.	IEEE Transactions on Signal Processing	2009	DBLP DOI BibTeX RDF
2	Bertil Schmidt, Douglas L. Maskell	Workshop on Using Emerging Parallel Architectures for Computational Science.	ICCS	2009	DBLP DOI BibTeX RDF	High Performance Computing, Reconfigurable Computing, Computational Science, GPGPU, Parallel Computer Architectures, Heterogeneous Multi-cores
2	Friman Sánchez, Alex Ramírez, Mateo Valero	Quantitative analysis of sequence alignment applications on multiprocessor architectures.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	bioinformatics applications, parallel architectures, multiprocessor architectures, sequence comparison
2	Muthu Manikandan Baskaran, Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan	Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories.	PPOPP	2008	DBLP DOI BibTeX RDF	graphics processor unit, multi-level tiling, scratchpad memory, data movement
2	Weirong Zhu, Yanwei Niu, Guang R. Gao	Performance portability on EARTH: a case study across several parallel architectures.	Cluster Computing	2007	DBLP DOI BibTeX RDF	Code portability, Programming execution model, Fine-grained multithreading, EARTH, Performance portability
2	Randy Smith, Dan Gibson, Shijin Kong	To CMP or not to CMP: analyzing packet classification on modern and traditional parallel architectures.	ANCS	2007	DBLP DOI BibTeX RDF	chip multiprocessors, packet classification
2	John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic	RAMP: Research Accelerator for Multiple Processors.	IEEE Micro	2007	DBLP DOI BibTeX RDF	field-programmable gate arrays, distributed systems, integration, parallel architectures, transactional memory, emulation, distributed-shared memory, hardware-software codesign, modeling of computer architecture
2	Pablo Toharia, Oscar David Robles, José Luis Bosque, Angel Rodríguez	Video Shot Extraction on Parallel Architectures.	ISPA	2006	DBLP DOI BibTeX RDF
2	Jason M. McGuiness, Colin Egan, Bruce Christianson, Guang Gao	The Challenges of Efficient Code-Generation for Massively Parallel Architectures.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
2	Marcus Randall, Andrew Lewis	An Extended Extremal Optimisation Model for Parallel Architectures.	e-Science	2006	DBLP DOI BibTeX RDF	evolutionary and adaptive dynamics, extremal optimisation, parallel architectures
2	Tomasz Madajczak	Taking Advantage of the SHECS-Based Critical Sections in the Shared Memory Parallel Architectures.	PPAM	2005	DBLP DOI BibTeX RDF
2	Weirong Zhu, Yanwei Niu, Guang R. Gao	Performance Portability on EARTH: A Case Study across Several Parallel Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Erik R. Altman, James C. Dehnert, Christoph W. Kessler, Jens Knoop (eds.)	Scheduling for Parallel Architectures: Theory, Applications, Challenges	Scheduling for Parallel Architectures	2005	DBLP BibTeX RDF
2	Scott Schneider, Christos D. Antonopoulos, Dimitrios S. Nikolopoulos	Factory: An Object-Oriented Parallel Programming Substrate for Deep Multiprocessors.	HPCC	2005	DBLP DOI BibTeX RDF	Multithreading substrate, Object-oriented parallel programming, Deep parallel architectures, Multiparadigm parallelism, Portability, Programmability
2	Arash Reyhani-Masoleh, M. Anwar Hasan	Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2^{m}).	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
2	Ming Huo, Shikharesh Majumdar	Performance of parallel architectures for CORBA-based systems.	WOSP	2004	DBLP DOI BibTeX RDF	CORBA performance, high performance middleware, interaction architectures
2	Ram Rangan, Neil Vachharajani, Manish Vachharajani, David I. August	Decoupled Software Pipelining with the Synchronization Array.	IEEE PACT	2004	DBLP DOI BibTeX RDF
2	Ceyda Oguz, Yu-Fai Fung, Muhammet Fikret Ercan, X. T. Qi	Parallel Genetic Algorithm for a Flow-Shop Problem with Multiprocessor Tasks.	ICCSA	2003	DBLP DOI BibTeX RDF	Genetic algorithms, parallel computing, parallel architectures
2	Patrice Quinton, Tanguy Risset	Structured Scheduling of Recurrence Equations: Theory and Practice.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF	parallelization of loop nests, structured recurrence equations, automatic synthesis of parallel architectures, parallel VLSI architectures, scheduling
2	Francisco J. González-Castaño, Ubaldo M. García-Palomares, José Luis Alba-Castro, José M. Pousada Carballo	Fast image recovery using dynamic load balancing in parallel architectures, by means of incomplete projections.	IEEE Transactions on Image Processing	2001	DBLP DOI BibTeX RDF
2	Lasse Natvig	Simulating Parallel Architectures with BSPlab.	HPCN	2001	DBLP DOI BibTeX RDF
2	Nicola Zingirian, Massimo Maresca	Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures.	CAMP	2000	DBLP DOI BibTeX RDF	loop regularization, instruction level parallel architectures, instruction reordering, image processing, embedded systems, embedded systems, video processing, digital signal processors, register renaming
2	Yingchun Zhu, Laurie J. Hendren	Locality Analysis for Parallel C Programs.	IEEE Trans. Parallel Distrib. Syst.	1999	DBLP DOI BibTeX RDF	compiling for parallel architectures, multithreaded architectures, Locality analysis
2	Masahiro Yasugi, Shegeyuki Eguchi, Kazuo Taki	Eliminating Bottlenecks on Parallel Systems using Adaptive Objects.	IEEE PACT	1998	DBLP DOI BibTeX RDF	bottleneck elimination, adaptive object, distributed shared object, mutual exclusion, parallel language, concurrent access, method dispatch
2	Zhao Wu, Wayne Wolf	Design Study of Shared Memory in VLIW Video Signal Processors.	IEEE PACT	1998	DBLP DOI BibTeX RDF	VSP, stride prediction table, cache, shared memory, VLIW, trace-driven simulation, memory system, stream buffer, multi-cluster
2	Dingchao Li, Yuji Iwahori, Tatsuya Hayashi, Naohiro Ishii	A Spill Code Placement Framework for Code Scheduling.	LCPC	1998	DBLP DOI BibTeX RDF	Fine grain parallel architectures, program behavior analysis, compiler optimization, register spilling, code scheduling
2	Fabrizio Petrini, Marco Vanneschi	k -ary n -trees: High Performance Networks for Massively Parallel Architectures. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	k-ary n-trees, flowcontrol, congestion-free patterns, routing, Interconnection networks, virtual channels, fat-trees
2	Kiyoharu Aizawa, Takayuki Hamamoto, Yasuhiro Ohtsuka, Mitsutoshi Hatori, M. Abe	Implementations of on Sensor Image Compression and Comparisons Between Pixel and Column Parallel Architectures. (PDF / PS)	ICIP	1997	DBLP DOI BibTeX RDF	sensor image compression, column parallel architecture, image signal, high pixel rate sensing, conditional replenishment, moving areas encoding, pixel parallel architecture, performance, image coding
2	Fabio Ancona, Stefano Rovetta, Rodolfo Zunino	High performance in tree-based parallel architectures.	EUROMICRO	1997	DBLP DOI BibTeX RDF	tree-based parallel architectures, integrated schema, complex node, dual-port memory, bidirectional high-speed communication link, tree-structured processor hierarchies, memory speed, experimental development, associative models, performance evaluation, optimality, connectivity, high performance, transputers
2	Jonas Skeppstedt	Overcoming Limitations of Prefetching in Multiprocessors by Compiler-Initiated Coherence Actions.	IEEE PACT	1997	DBLP DOI BibTeX RDF	compiler-initiated coherence, CC-NUMA multiprocessor, compiler-controlled prefetching, read-stall time, write-latency, read-latency, memory access latency reduction, migratory sharing, parallel architectures, multiprocessors, prefetching, prefetch, compiler-analysis
2	Fabrizio Petrini, Marco Vanneschi	Efficient Personalized Communication on Wormhole Networks.	IEEE PACT	1997	DBLP DOI BibTeX RDF	parallel architectures and computation models, k-ary n-trees, performance evaluation, interconnection networks, k-ary n-cubes, BSP, h-relations
2	S. R. Subramanya	A Parallel Algorithm with Embedded Load Balancing for Autocorrelation Matrix Computation.	ISPAN	1997	DBLP DOI BibTeX RDF
2	H. Tanaka	Toward more advanced usage of instruction level parallelism by a very large data path processor architecture.	ISPAN	1997	DBLP DOI BibTeX RDF	very large data path processor, instruction analysis, parallel gain, parallel architectures, microprocessor, instruction level parallelism, processor architecture, performance gain
2	D. J. Kaplan	An introduction to the processing graph method.	ECBS	1997	DBLP DOI BibTeX RDF	processing graph method, MIMD message passing parallel architectures, message passing, system designer
2	Jing-Chiou Liou, Michael A. Palis	A Comparison of General Approaches to Multiprocessor Scheduling. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	two phase method, task clustering, near optimal number of processors, task clustering algorithm, cluster merging, communication traffic minimizing, CTM, distributed memory parallel architectures, load balancing, multiprocessing systems, multiprocessor scheduling, task graphs, task graph scheduling
2	Elizabeth M. Rudnick, Janak H. Patel	Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation.	VLSI Design	1997	DBLP DOI BibTeX RDF	serial logic simulation bottleneck, parallel fault simulation, sequential circuit fault simulation algorithms, fault-partitioning approach, test set partitioning, parallel architectures, logic CAD, fault coverage, speedup, benchmark circuits
2	Michael A. Palis, Jing-Chiou Liou, David S. L. Wei	Task Clustering and Scheduling for Distributed Memory Parallel Architectures.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	Program task graph, task granularity, approximation algorithms, task scheduling, distributed memory architectures
2	Oum-El-Kheir Benkahla, Chouki Aktouf, Chantal Robach	System-Diagnosis of Cluster-Based Parallel Architectures.	PDP	1996	DBLP DOI BibTeX RDF
2	Hiroyuki Hashimoto, Hiroshi Masuyama, Toshihiko Sasama	Fault tolerant subcube allocation in hypercube.	ISPAN	1996	DBLP DOI BibTeX RDF	subcube allocation, fault-free subcubes, fault tolerant, parallel architectures, fault tolerant computing, hypercube, hypercube networks, degradation, faulty hypercubes
2	Jae-dong Lee, Kenneth E. Batcher	A bitonic sorting network with simpler flip interconnections.	ISPAN	1996	DBLP DOI BibTeX RDF	flip interconnections, bitonic sorting network, inter-level wiring, parity technique, Construct-BSMF, N/2 even-parity keys, interconnection scheme, perfect-shuffle interconnection, parallel algorithms, parallel architectures, multiprocessor interconnection networks, sorting
2	Byoung Seob Park, Sung Chun Kim	FBSF: a new fast packet switching fabric based-on multistage interconnection network with multiple outlets.	ISPAN	1996	DBLP DOI BibTeX RDF	packet switching fabric, FBSF, multiple outlets, ATM switch architecture, FAB Banyan Switching Fabrics, Batcher sorter, radix-r double shuffle network, r-packet distributors, parallel architectures, packet switching, multistage interconnection networks, multistage interconnection network, switch fabrics
2	Hui-Ling Huang, Gen-Huey Chen	Shortest-path routing algorithm and topological properties for two-level hypernet networks.	ISPAN	1996	DBLP DOI BibTeX RDF	hypernet, recursively scalable networks, parallel architectures, connectivity, multiprocessor interconnection networks, embedding, diameter, shortest-path routing, topological properties
2	Richard F. Freund, Taylor Kidd, Debra A. Hensgen, Lantz Moore	SmartNet: a scheduling framework for heterogeneous computing.	ISPAN	1996	DBLP DOI BibTeX RDF	SmartNet, scheduling framework, scheduling, optimization, load balancing, parallel architectures, distributed processing, processor scheduling, heterogeneous computing, distributed environments, heterogeneous environment, shared resource
2	K. P. Lam, A. Furness	On parallelization of neural classification algorithms.	ISPAN	1996	DBLP DOI BibTeX RDF	neural classification algorithms, neural classifier architecture, neural architectures, VLSI processing model, neural networks, parallelization, parallel computation, parallel architectures, pattern classification, neural net architecture
2	Issei Numata, Susumu Horiguchi	Efficient reconfiguration scheme for mesh-connected network: the recursive shift approach.	ISPAN	1996	DBLP DOI BibTeX RDF	mesh-connected network, recursive shift, faulty processing elements, mesh arrays, redundant processing elements, fault tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, reconfigurable architectures, massively parallel system, reconfiguration scheme
2	Venkatavasu Bokka, Stephan Olariu, James L. Schwing, Larry Wilson, Albert Y. Zomaya	A time-optimal solution to planar point location in ordered functional domains, with applications.	ISPAN	1996	DBLP DOI BibTeX RDF	time-optimal solution, ordered functional domains, I/O time, parallel algorithms, computational complexity, parallel architectures, CAD, mesh, processing time, continuous functions, planar point location
2	H. Fukumori, Y. Kono, K. Nishimatsu, Y. Muraoka	Finite element analysis with heterogeneous parallel computer environment over ATM network.	ISPAN	1996	DBLP DOI BibTeX RDF	FEM solver, heterogeneous parallel environment, Fujitsu AP1000, NEC Cenju-3, OLU, parallel triangular mesh generator, substructure method, parallel algorithms, parallel computers, parallel architectures, Delaunay Triangulation, mesh generation, finite element analysis
2	Zhiwei Xu, Kai Hwang	MPPs and clusters for scalable computing.	ISPAN	1996	DBLP DOI BibTeX RDF	scalable parallel computing, Cray T3D/T3E, ASCI TeraFLOPS, performance evaluation, scalability, parallel architectures, reconfigurable architectures, clusters of workstations, Intel Paragon, Intel, massively parallel processors, performance attributes, scalable computing, MPPs, IBM SP2
2	Yiqun Ge, David Y. Y. Yun	A Method that Determines Optimal Grain Size and Inherent Parallelism Concurrently.	ISPAN	1996	DBLP DOI BibTeX RDF	Grain Packing, 2D Compression, Scheduling, Multiple Objectives, Inherent Parallelism
2	Mounir Hamdi, Yi Pan	Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses.	ISPAN	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations
2	Chi-Hsiang Yeh, Behrooz Parhami	Hierarchical Swapped Networks: Efficient Low-Degree Alternatives to Hypercubes and Generalized Hypercubes.	ISPAN	1996	DBLP DOI BibTeX RDF	algorithm emulation, ascend/descend algorithms, optimal diameter, interconnection networks, parallel architectures, hierarchical networks
2	Hong Shen	Fault-tolerant multicast with traffic-balancing in hypercubes.	ISPAN	1996	DBLP DOI BibTeX RDF	traffic-balancing, fault-tolerant multicast, fault-tolerant multicasting, computational complexity, parallel architectures, fault tolerant computing, hypercubes, time complexity, hypercube networks, interprocessor communication, hypercube computers
2	Kemal Efe, Antonio Fernández	Mesh-Connected Trees: A Bridge Between Grids and Meshes of Trees.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	parallel algorithms, grids, interconnection networks, Parallel architectures, hypercubes, binary tree, graph embedding, product networks, mesh of trees
2	Tonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth	Analog VLSI circuits for manufacturing inspection.	ARVLSI	1995	DBLP DOI BibTeX RDF	analog VLSI circuits, manufacturing inspection, programmable structuring elements, oriented edge detection, high speed preprocessors, serial/parallel processing, focal-plane processing, vertical bipolar phototransistors, digital CMOS process, adaptive image threshold, 2.0 micron, computer vision, VLSI, edge detection, mathematical morphology, machine vision, manufacture, morphological operations, selective attention, massively parallel architectures, CMOS analogue integrated circuits, automatic optical inspection, focal planes, analogue processing circuits
2	Anthony D. Johnson	On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	locally optimal breaking strategy, nondisjoint cyclic vertical constraints, VLSI channel routing, vertical constraint graph, nondisjoint circuits, common vertex, common path, channel router heuristics, automatic routers, interactive routers, VLSI, graph theory, parallel architectures, network routing, circuit layout CAD, integrated circuit layout
2	Philip J. Morrow, Danny Crookes	Using Prolog to implement a compiler for a parallel image processing language. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	parallel image processing language, BNF syntax definition, image processing, compiler, parallel architectures, parallel architectures, PROLOG, programming languages, program compilers, parallel languages, software portability, software portability, abstract model, implementation language
2	Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, Prithviraj Banerjee	Parallel algorithms for logic synthesis using the MIS approach. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	combinational logic synthesis, VLSI system design, ProperMIS, portable parallel algorithm, parallel algorithms, parallel algorithms, parallel architectures, logic design, combinational circuits, logic synthesis, logic CAD
2	Hatem Sellami, Sudhakar Yalamanchili	Time scale combining of conservative parallel discrete event simulations. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	time scale combining, inter-processor communication messages, distinct simulations, simulation trials, parallel processing, parallel architectures, discrete event simulation, discrete event simulations, parallel discrete event simulations
2	Kemal Efe, Antonio Fernández	Products of Networks with Logarithmic Diameter and Fixed Degree.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF	application specific array processors, interconnection networks, parallel architectures, multiprocessors, emulation, graph embedding, Product networks, embedded architectures
2	Hiecheol Kim, Jean-Luc Gaudiot	Exploitation of Fine-grain Parallelism in Logic Languages on Massively Parallel Architectures.	IFIP PACT	1994	DBLP BibTeX RDF
2	David M. Nicol, Albert G. Greenberg, Boris D. Lubachevsky	Massively Parallel Algorithms for Trace-Driven Cache Simulations.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	massively parallel algorithms, trace-driven cache simulations, least-recently-used policy, EREW parallel model, algorithm timings, reference-based line replacement policies, least-frequently-used policy, random replacement policy, space overhead, SIMD implementation, parallel algorithms, computational complexity, parallel architectures, trace, buffer storage, program diagnostics, simulation algorithm, MasPar MP-1
2	John T. O'Donnell	Data Parallel Implementation of Extensible Sparse Functional Arrays.	PARLE	1993	DBLP DOI BibTeX RDF
2	Bapiraju Vinnakota, Niraj K. Jha	Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	algorithm-based fault-tolerant systems, computation-intensive tasks, ABFT scheme, synthesis method, fault-tolerant median filter, reliability, graph theory, parallel architectures, fault tolerant computing, dependence graphs, parallelarchitectures
2	Jean-Marc Jézéquel, F. André Bergheul, F. André	Programming Massively Parallel Architectures with Sequential Object Oriented Languages.	PARLE	1992	DBLP DOI BibTeX RDF	Object oriented languages, Massively parallel systems, Parallel programming paradigms
2	Arnold L. Rosenberg	Better Parallel Architectures via Emulations.	Heinz Nixdorf Symposium	1992	DBLP DOI BibTeX RDF
2	Hua Bi	Explicit Expression of Multidimensional Data Parallelism.	PARLE	1992	DBLP DOI BibTeX RDF
2	Zbigniew Chamski	Generating Memory-Efficient Imperative Data Structures from Systolic Programs.	PARLE	1992	DBLP DOI BibTeX RDF
2	Rainer Feldmann, Juraj Hromkovic, Seshu Madhavapeddy, Burkhard Monien, Peter Mysliwietz	Optimal Algorithms for Disemination of Information in Generalized Communication Modes.	PARLE	1992	DBLP DOI BibTeX RDF
2	Gregory L. Heileman, Michael Georgiopoulos, William D. Roome	A General Framework for Concurrent Simulation of Neural Network Models.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	discrete event nonlinear dynamical systems, continuous-time differential equations, discrete-time difference equations, concurrent object-oriented discrete event simulation, data structures, object-oriented programming, parallel architectures, discrete event simulation, neural nets, object-oriented language, nonlinearities, parallel languages, data abstraction, neural network models, concurrent simulation, general-purpose parallel computer
2	Jean-Marc Jézéquel	EPEE: an Eiffel Environment to Program Distributed Memory Parallel Computers.	ECOOP	1992	DBLP DOI BibTeX RDF	Parallel Object Oriented Programming, Data Parallelism, Eiffel, Massively Parallel Architectures
2	Hussein M. Alnuweiri, Viktor K. Prasanna	Fast Image Labeling Using Local Operators on Mesh-Connected Computers.	IEEE Trans. Pattern Anal. Mach. Intell.	1991	DBLP DOI BibTeX RDF	bit-serial processors, local operators, asymptotic time complexity, very fast shift registers, parallel algorithm, parallel algorithms, computational complexity, computational complexity, parallel architectures, parallel architectures, computerised picture processing, computerised picture processing, stacks, communication links, mesh-connected computers, image labeling
2	Jianning Xu	Decomposition of Convex Polygonal Morphological Structuring Elements into Neighborhood Subsets.	IEEE Trans. Pattern Anal. Mach. Intell.	1991	DBLP DOI BibTeX RDF	convex polygonal morphological structuring elements, neighborhood subsets, neighborhood-processing-based parallel image computers, O(1) time algorithm, four-neighbor-connected mesh machines, optimal decomposition, 3*3 morphological operations, parallel architectures, parallel architectures, computerised picture processing, computerised picture processing, set theory, linear time algorithm
2	Anthony J. G. Hey	Experiments in MIMD Parallelism.	PARLE	1989	DBLP DOI BibTeX RDF
2	Giuseppe Marino, Giancarlo Succi	Data structures for parallel execution of functional languages.	PARLE	1989	DBLP DOI BibTeX RDF
2	Apostolos Nikolaos Refenes, Eugene Eberbach, Stephen C. McCabe, Philip C. Treleaven	PARLE: A Parallel Target Language for Integrating Symbolic and Numeric Processing.	PARLE	1989	DBLP DOI BibTeX RDF
2	Geoffrey L. Burn	Overview of a Parallel Reduction Machine Project II.	PARLE	1989	DBLP DOI BibTeX RDF