Search results for "parallel processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Andreas Svolos, Charalampos Konstantopoulos, Christos Kaklamanis	A Parallel Solution in Texture Analysis Employing a Massively Parallel Processor (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF	hypercube, texture analysis, co-occurrence matrix, massively parallel processor
3	Dirk Fimmel, Renate Merker	Propagation of I/O-Variables in Massively Parallel Processor Arrays.	PDP	1996	DBLP DOI BibTeX RDF	parallel processor arrays, systems of recurrence equations, automatic design methods, massive parallelism
3	Lorenz A. Schmitt, Stephen S. Wilson	The AIS-5000 Parallel Processor.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	AIS-5000, parallel memory organization, image-based algorithms, computer vision, computer vision, parallel architecture, parallel architectures, computerised picture processing, computerised picture processing, microprocessor chips, parallel processor, SIMD architecture
2	Dimitris Syrivelis, Spyros Lalis	Extracting Coarse-Grained Pipelined Parallelism Out of Sequential Applications for Parallel Processor Arrays.	ARCS	2009	DBLP DOI BibTeX RDF
2	David B. Thomas, Lee W. Howes, Wayne Luk	A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation.	FPGA	2009	DBLP DOI BibTeX RDF	mppa, fpga, monte-carlo, random numbers, gpu
2	Xingzhi Wen, Uzi Vishkin	Fpga-based prototype of a pram-on-chip processor.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	ease-of-programming, explicit multi-threading, on-chip parallel processor, pram, parallel algorithms, xmt
2	Ian Buck	GPU Computing: Programming a Massively Parallel Processor.	CGO	2007	DBLP DOI BibTeX RDF
2	Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement	Modeling of Interconnection Networks in Massively Parallel Processor Architectures.	ARCS	2007	DBLP DOI BibTeX RDF
2	Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich	Efficient event-driven simulation of parallel processor architectures.	SCOPES	2007	DBLP DOI BibTeX RDF	embedded tools, simulation, modeling, processor arrays
2	Shorin Kyo, Takuya Koga, Hanno Lieske, Shouhei Nomoto, Shin'ichiro Okazaki	A low-cost mixed-mode parallel processor architecture for embedded systems.	ICS	2007	DBLP DOI BibTeX RDF	embedded systems, parallel architectures, SIMD, MIMD, multimedia processing, tile architectures, mixed-mode
2	Andrea Di Blas, David M. Dahle, Mark Diekhans, Leslie Grate, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Mark Kendrick, Francisco J. Mesa-Martinez, David Pease, Eric Rice, Angela Schultz, Don Speck, Richard Hughey	The UCSC Kestrel Parallel Processor.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	VLSI system design, image processing, Parallel processing, high performance computing, computer architecture, systolic array, SIMD, DNA, computational chemistry, biological sequence analysis
2	Arjuna Madanayake, Leonard T. Bruton	A high performance distributed-parallel-processor architecture for 3D IIR digital filters.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi	Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory.	AINA	2004	DBLP DOI BibTeX RDF
2	Sonny Tham, John Morris	Performance of the Achilles Router.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF	Parallel processor interconnection, cross-bar switching, networks of workstations
2	Stephanie McBader, Luca Clementel, Alvise Sartori, Andrea Boni, Peter Lee	SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor.	FPL	2002	DBLP DOI BibTeX RDF
2	Krishna Kumar Rangan, Philip A. Wilsey, Nilesh Pisolkar, Nael B. Abu-Ghazaleh	PPIM-SIM: An Efficient Simulator for a Parallel Processor in Memory.	Annual Simulation Symposium	2001	DBLP DOI BibTeX RDF
2	Saravut Charcranoon, Thomas G. Robertazzi, Serge Luryi	Parallel Processor Configuration Design with Processing/Transmission Costs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	single-level tree network, local search, economics, Cost, heuristic algorithm, divisible load, star network
2	Andreas Svolos, Charalampos Konstantopoulos, Christos Kaklamanis	fficient Binary Morphological Algorithms on a Massively Parallel Processor. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	hypercube, mathematical morphology, dilation, massively parallel processor, erosion, associative processor
2	Ken'ichirou Kimura, Hirofumi Amano, Akifumi Makinouchi	Dynamic Performance Optimization Mechanism for Parallel Object-Oriented Database Programming Languages. (PDF / PS)	IDEAS	2000	DBLP DOI BibTeX RDF	dynamic performance optimization, parallel object-oriented database programming languages, distributed-memory parallel processor, remote object referencing, biased distribution, object relocation, simulation tests, topology, parallel languages, performance degradation, inter-processor communication, load imbalance, object allocation
2	Albert Y. Zomaya, Chris Ward, Benjamin S. Macey	Genetic Scheduling for Parallel Processor Systems: Comparative Studies and Performance Issues.	IEEE Trans. Parallel Distrib. Syst.	1999	DBLP DOI BibTeX RDF	Genetic algorithms, scheduling, parallel processing, heuristics, randomization
2	Thomas Schmitt, Dirk Fimmel, Mathias Kortke, Renate Merker	Parallel Processor Array for Tomographic Reconstruction Algorithms.	EUROCAST	1999	DBLP DOI BibTeX RDF
2	David C. Wong, Edward W. Davis, Jeffrey O. Young	A Software Approach to Avoiding Spatial Cache Collisions in Parallel Processor Systems.	IEEE Trans. Parallel Distrib. Syst.	1998	DBLP DOI BibTeX RDF	Cache collision, cache offset, highly parallel systems, sequential DO-loops, direct-mapped cache
2	Albert Y. Zomaya, Matthew Clements, Stephan Olariu	A Framework for Reinforcement-Based Scheduling in Parallel Processor Systems.	IEEE Trans. Parallel Distrib. Syst.	1998	DBLP DOI BibTeX RDF	scheduling, Neural networks, parallel processing, reinforcement learning, randomization, task allocation
2	Albert Y. Zomaya, Matthew Clements, Stephan Olariu	Randomized Reinforcement Based Scheduling In Parallel Processor Systems.	HICSS	1997	DBLP DOI BibTeX RDF
2	Renate Merker, Ulrich Eckhardt, Dirk Fimmel, H. Schreiber	A System for Designing Parallel Processor Arrays.	EUROCAST	1997	DBLP DOI BibTeX RDF
2	Albert Y. Zomaya, Chris Ward, Benjamin S. Macey	An Evolutionary Approach for Scheduling in Parallel Processor Systems.	ISPAN	1997	DBLP DOI BibTeX RDF	Genetic algorithms, scheduling, load balancing, parallel processing
2	Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr.	Realization of a nonlinear digital filter on a DSP array processor.	ASAP	1997	DBLP DOI BibTeX RDF	nonlinear digital filter, third-order Volterra digital filtering algorithm, AT&T DSP-3 parallel processor, nonlinear communication channel equalization, 64-QAM signal constellation, performance evaluation, digital signal processing chips, time-skewing
2	Mun Choon Chan, Giovanni Pacifici, Rolf Stadler	Prototyping Network Architectures on a Supercomputer. (PDF / PS)	HPDC	1996	DBLP DOI BibTeX RDF	network architecture prototyping, dynamic behavior evaluation, overall performance evaluation, functional properties, interactive emulation platform, multimedia network services, load patterns, network management operations, KSR-1, SP2 parallel processor, graphics workstation, ATM links, performance evaluation, real-time systems, parallel programming, interactive systems, multimedia communication, data visualisation, supercomputer, software prototyping, software prototype, network operating systems, telecommunication computing, network control systems, engineering graphics, telecommunication network management, telecommunication control, real-time visualization, network sizes, dynamic properties, control system CAD
2	Eric A. Brewer, Paul Gauthier, Armando Fox, Angela Schuett	Software Techniques for Improving MPP Bulk-Transfer Performance. (PDF / PS)	IPPS	1996	DBLP DOI BibTeX RDF	software techniques, bulk-transfer performance, traffic interleaving, Thinking Machines CM-5, one-on-one communication, MIT Alewife machine, token-passing scheme, distributed dynamic scheduling, irregular traffic patterns, traffic massaging, near-permutations, performance evaluation, parallel machines, processor scheduling, software performance evaluation, telecommunication traffic, preprocessing, barriers, network congestion, algorithm performance, Intel Paragon, static scheduling, massively parallel processor, global state
2	Rainer Hauser, Reinhard Männer, Mikhail Makhaniok	NERV: a parallel processor for standard genetic algorithms. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	standard genetic algorithms, MIMD multiprocessor system, NERV hardware, NERV multiprocessor, genetic algorithms, parallel algorithms, parallel architectures, parallel machines, GA, parallel processor, parallel genetic algorithms
2	Giuseppe Ascia, Vincenzo Catania	Design of a VLSI parallel processor for fuzzy computing.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI parallel processor, fuzzy computing, /spl alpha/-level sets theory, memory resources, processing units, 50 MHz, scalability, VLSI, parallelism, fuzzy logic, parallel architectures, inference mechanisms, fuzzy set theory, integrated circuit design, microprocessor chips, membership functions, fuzzy inferences, clock frequency, 8 bit
2	Arindam Saha	A simulator for real-time parallel processing architectures.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	real-time parallel processing architectures, time-driven flit-based wormhole-routed parallel processor network simulator, user-friendly graphical user interface, prioritized queues, resource allocation policies, message priorities, average latency convergence, throughput monitoring, communication characteristics, performance, real-time systems, resource allocation, parallel architectures, graphical user interfaces, virtual machines, concurrency control, convergence, deadlocks, virtual channel, overlaps, real-time networks
2	J. A. Lupo	Benchmarking UHGROMOS.	HICSS	1995	DBLP DOI BibTeX RDF	GROMOS, parallel Fortran preprocessor, Pfortran, Intel Corporation, IBM Corporation, massively parallel processor machines, Intel iPSC/860, Caltech Intel DELTA, IBM SP1, UHGROMOS molecular dynamics program, test application, parallel performance analysis, parallel programming, benchmarking, FORTRAN, parallel machines, parallel machines, software performance evaluation, physics, parallel languages, software portability, physics computing, porting, Intel Paragon, program processors, molecular dynamics method
2	Ranga S. Ramanujan, Jordan Bonney, Kenneth J. Thurber	Network Shared Memory: A New Approach for Clustering Workstations for Parallel Processing. (PDF / PS)	HPDC	1995	DBLP DOI BibTeX RDF	network shared memory, clustering workstations, shared memory parallel processor, performance evaluation, performance evaluation, parallel processing, parallel processing, shared memory systems, implementation model
2	Dejan S. Milojicic, David L. Black, Steven J. Sears	Operating system support for concurrent remote task creation. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	concurrent remote task creation, application startup, multiple nodes, remote task creation, multiple remote tasks, distributed virtual memory, paging path, operating systems, distributed memory systems, operating system kernels, virtual storage, massively parallel processor, Mach
2	Su-Hui Chiang, Rajesh K. Mansharamani, Mary K. Vernon	Use of Application Characteristics and Limited Preemption for Run-to-Completion Parallel Processor Scheduling Policies.	SIGMETRICS	1994	DBLP DOI BibTeX RDF
2	Ahmed Louri	An Optical Content-Adressable Parallel Processor for Fast Searching and Retrieving.	PARLE	1991	DBLP DOI BibTeX RDF
2	R. L. Shoemaker, Harrison H. Barrett, R. H. Seacat III	TRIMM: A Parallel Processor for Image Reconstruction by Simulated Annealing.	PPSN	1990	DBLP DOI BibTeX RDF
2	A. L. Kimball, Raimond L. Winslow	Modeling the retinal horizontal cell layer on a massively parallel processor: a detailed neural network model.	SPDP	1990	DBLP DOI BibTeX RDF
2	M. R. Brown, S. DasGupta	Design of a general purpose meta-assembler for parallel processor environment in ISPS.	Annual Simulation Symposium	1989	DBLP DOI BibTeX RDF	ISPS
2	Tomoo Fukazawa, Takashi Kimura, Masaaki Tomizawa, Kazumitsu Takeda, Yoshitaka Itoh	R256: A Research Parallel Processor for Scientific Computation.	ISCA	1989	DBLP DOI BibTeX RDF
2	Kazuaki Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita	The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures.	ICS	1989	DBLP DOI BibTeX RDF
2	Len Dekker, Edward E. E. Frietman	Optical link and processor clustering in the Delft parallel processor.	ICS	1988	DBLP DOI BibTeX RDF
2	Falk-D. Kübler, Friedrich Lücking	Cluster oriented architecture for the mapping of parallel processor networks to high performance applications.	ICS	1988	DBLP DOI BibTeX RDF
2	Edward W. Davis	Application of the massively parallel processor to database management systems.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF
2	Gary J. Nutt	A parallel processor for evaluation studies.	AFIPS National Computer Conference	1976	DBLP DOI BibTeX RDF
2	Jack L. Rosenfeld	A case study in programming for parallel-processors.	Commun. ACM	1969	DBLP DOI BibTeX RDF	Gauss-Seidel, Jacobi, storage interference, simulation, parallel programming, parallelism, multiprocessor, convergence, tasking, multiprogramming, relaxation, parallel-processor, electrical network
1	Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim	3D-MAPS: 3D Massively parallel processor with stacked memory.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Georgios Chatziparaskevas, Andreas Brokalakis, Ioannis Papaefstathiou	An FPGA-based parallel processor for Black-Scholes option pricing using finite differences schemes.	DATE	2012	DBLP BibTeX RDF
1	Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto	A Scalable Massively Parallel Processor for Real-Time Image Processing.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Anteneh A. Abbo, Richard P. Kleihorst, Ben Schueler	Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis.	Signal Processing Systems	2011	DBLP DOI BibTeX RDF
1	J. W. Bosman, Rob van der Mei, Gerard Hoekstra	Poster: optimal dispatching policies for parallel processor sharing nodes with partial information.	SIGMETRICS Performance Evaluation Review	2011	DBLP DOI BibTeX RDF
1		Massively Parallel Processor (MPP).	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Suneil Mohan, Aalap Tripathy, Amitava Biswas, Rabi N. Mahapatra	Parallel Processor Core for Semantic Search Engines.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Vahid Lari, Frank Hannig, Jürgen Teich	Distributed Resource Reservation in Massively Parallel Processor Arrays.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich	Decentralized dynamic resource management support for massively parallel processor arrays.	ASAP	2011	DBLP DOI BibTeX RDF
1	Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto	A scalable massively parallel processor for real-time image processing.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Claus Traulsen, Reinhard von Hanxleden	Reactive parallel processing for synchronous dataflow.	SAC	2010	DBLP DOI BibTeX RDF	Scade, reactive processors, synchronous languages, parallel execution, synchronous dataflow, Lustre
1	Wei Hu, Zhao Dong, Ivo Ihrke, Thorsten Grosch, Guodong Yuan, Hans-Peter Seidel	Interactive volume caustics in single-scattering media.	SI3D	2010	DBLP DOI BibTeX RDF	volume caustics, real-time rendering, ray marching
1	Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, Miguel Arias-Estrada	Parallel Processor for 3D Recovery from Optical Flow.	Int. J. Reconfig. Comp.	2009	DBLP DOI BibTeX RDF
1	Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera	High Performance Image Processing on a Massively Parallel Processor Array.	DSD	2009	DBLP DOI BibTeX RDF
1	Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis	Optical Flow on the Ambric Massively Parallel Processor Array (MPPA).	FCCM	2009	DBLP DOI BibTeX RDF	MPPA, FPGA, Optical Flow, Reconfigurable Computing
1	Dimitris Syrivelis, Spyros Lalis	Supporting Multitasking of Pipelined Computations on Embedded Parallel Processor Arrays.	ICPP Workshops	2009	DBLP DOI BibTeX RDF
1	George C. Caragea, A. Beliz Saybasili, Xingzhi Wen, Uzi Vishkin	Brief announcement: performance potential of an easy-to-program PRAM-on-chip prototype versus state-of-the-art processor.	SPAA	2009	DBLP DOI BibTeX RDF	ease of programming, explicit multi-treading, on-chip parallel processor, paraleap, parallel algorithms, PRAM, xmt
1	Anna Nepomniaschaya	Associative Version of the Ramalingam Decremental Algorithm for Dynamic Updating the Single-Sink Shortest-Paths Subgraph.	PaCT	2009	DBLP DOI BibTeX RDF	Directed weighted graph, subgraph of the shortest paths, decremental algorithm, associative parallel processor, access data by contents, adjacency matrix
1	Qing Li, Kip Macy	Optimizing the BSD routing system for parallel processing.	PRESTO	2009	DBLP DOI BibTeX RDF	arp, flow table, mp, neighbor cache, server load balancing (slb), smp, routing, synchronization, ipv6, freebsd, ip
1	Eduardo Argollo, Ayose Falcón, Paolo Faraboschi, Matteo Monchiero, Daniel Ortega	COTSon: infrastructure for full system simulation.	Operating Systems Review	2009	DBLP DOI BibTeX RDF
1	Michael Butts, Brad Budlong, Paul Wasson, Ed White	Reconfigurable Work Farms on a Massively Parallel Processor Array.	FCCM	2008	DBLP DOI BibTeX RDF
1	Martin Hülse, David Robert Wallace Barr, Piotr Dudek	Cellular automata and non-static image processing for embodied robot systems on a massively parallel processor array.	Automata	2008	DBLP BibTeX RDF
1	Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, Miguel Arias-Estrada	Parallel Processor for 3D Recovery from Optical Flow.	ReConFig	2008	DBLP DOI BibTeX RDF
1	Erik Lindholm, John Nickolls, Stuart F. Oberman, John Montrym	NVIDIA Tesla: A Unified Graphics and Computing Architecture.	IEEE Micro	2008	DBLP DOI BibTeX RDF	SIMT, unified graphics and parallel computing architecture, cooperative thread array, GPU, graphics processing unit, SIMD, parallel processor, Tesla, Hot Chips 19
1	Stanley Tzeng, Li-Yi Wei	Parallel white noise generation on a GPU via cryptographic hash.	SI3D	2008	DBLP DOI BibTeX RDF	GPU techniques, parallel computation, texturing, noise, random number generation
1	Shorin Kyo, Shin'ichiro Okazaki	In-vehicle vision processors for driver assistance systems.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Mahmood Ahmadi, Stephan Wong	An Approach for Optimal Bandwidth Allocation in Packet Processing Systems.	CNSR	2008	DBLP DOI BibTeX RDF
1	Xiaoyong Wen, Faycal Bensaali, Reza Sotudeh	Dynamic Co-operative Intelligent Memory.	DELTA	2008	DBLP DOI BibTeX RDF
1	James S. Tandon, Steven E. Butner	Bounding Communication Energy Overhead in Parallel Networks with Power-Delay Scalability.	ICPADS	2008	DBLP DOI BibTeX RDF
1	Thomas M. DuBois, Bryant Lee, Yi Wang, Marc Olano, Uzi Vishkin	XMT-GPU: A PRAM Architecture for Graphics Computation.	ICPP	2008	DBLP DOI BibTeX RDF
1	Olav Lysne, José Miguel Montañana, Jose Flich, José Duato, Timothy Mark Pinkston, Tor Skeie	An Efficient and Deadlock-Free Network Reconfiguration Protocol.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Interconnections (Subsystems), Topology, I/O and Data Communications
1	Carlos Pérez-Vidal, Luis Gracia, Nicolás García Aracil, José Maria Sabater, José Maria Azorín, J. de Gea	On Accelerating the ss-Kalman Filter for High-Performance Computation.	DCAI	2008	DBLP DOI BibTeX RDF	steady state Kalman filter, FPGA, Parallel implementation
1	Manoel T. F. Cunha, Jose C. F. Telles, Alvaro L. G. A. Coutinho	On the Implementation of Boundary Element Engineering Codes on the Cell Broadband Engine.	VECPAR	2008	DBLP DOI BibTeX RDF	Parallel Programming, SIMD, Vectorization, Cell Broadband Engine, Boundary Element Method, Boundary Elements
1	Richard Hughey, Andrea Di Blas	Finding the Next Computational Model: Experience with the UCSC Kestrel.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	biological sequence comparison, VLSI system design, application-specific array processor, parallel processing, parallel programming, computer architecture, systolic array, SIMD, sequence analysis, shared registers
1	Mike Butts	Synchronization through Communication in a Massively Parallel Processor Array.	IEEE Micro	2007	DBLP DOI BibTeX RDF	multiple data stream processors, synchronization, parallel architectures, multiprocessors, multicore architectures
1	Richard P. Kleihorst, Anteneh A. Abbo, Ben Schueler, Alexander Danilin	Camera mote with a high-performance parallel processor for real-time frame-based video processing.	AVSS	2007	DBLP DOI BibTeX RDF
1	Richard P. Kleihorst, Anteneh A. Abbo, Ben Schueler, Alexander Danilin	Camera Mote with a High-Performance Parallel Processor for Real-Time Frame-Based Video Processing.	ICDSC	2007	DBLP DOI BibTeX RDF
1	Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier	Massively Parallel Processor Architectures: A Co-design Approach.	ReCoSoC	2007	DBLP BibTeX RDF
1	Xingzhi Wen, Uzi Vishkin	PRAM-on-chip: first commitment to silicon.	SPAA	2007	DBLP DOI BibTeX RDF	ease-of-programming, explicit multi-threading, on-chip parallel processor, parallel algorithms, PRAM, XMT
1	Wenjun Xiao, Behrooz Parhami	A Group Construction Method with Applications to Deriving Pruned Interconnection Networks.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	geometric group theory, parallel processor architecture, pruning scheme, VLSI realization, distributed system, interconnection network, Cayley graph, network diameter, Algebraic structure
1	Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita	Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier".	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	David Robert Wallace Barr, Piotr Dudek, Jonathan M. Chambers, Kevin N. Gurney	Implementation of multi-layer leaky integrator networks on a cellular processor array.	IJCNN	2007	DBLP DOI BibTeX RDF
1	Kevin Schaffer, Robert A. Walker	A Prototype Multithreaded Associative SIMD Processor.	IPDPS	2007	DBLP DOI BibTeX RDF
1	David López Vilariño, Piotr Dudek	Evolution of Pixel Level Snakes towards an efficient hardware implementation.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon	Parallel Asynchronous Watershed Algorithm-Architecture.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	Asynchronous algorithm-architecture, performance evaluation, image segmentation, hill-climbing, correctness proof, parallel processors, watershed
1	Jan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit	Image Quantisation on a Massively Parallel Embedded Processor.	SAMOS	2007	DBLP DOI BibTeX RDF
1	Toru Shimizu, Masami Nakajima, Masahiro Kainaga	Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Matthew Papakipos	Innovative technologies I - Unleash the power of stream processors with a new software platform for commodity hardware.	SC	2006	DBLP DOI BibTeX RDF
1	Arun Kejariwal, Alexandru Nicolau, Hideki Saito, Xinmin Tian, Milind Girkar, Utpal Banerjee, Constantine D. Polychronopoulos	A general approach for partitioning N-dimensional parallel nested loops with conditionals.	SPAA	2006	DBLP DOI BibTeX RDF	partitioning, conditionals, parallel loops, affine, Fourier-Motzkin elimination
1	Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger	A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing.	ASAP	2006	DBLP DOI BibTeX RDF
1	Richard Hughey, Andrea Di Blas	The UCSC Kestrel Application-Unspecific Processor.	ASAP	2006	DBLP DOI BibTeX RDF
1	Sam Sander, Linda M. Wills	Retargeting Image-Processing Algorithms to Varying Processor Grain Sizes.	ICPP Workshops	2006	DBLP DOI BibTeX RDF
1	Jonathan Villanueva, Vianery Cruz, Gerardo Reyes, Aaron Benitez	Extracting Refined Rules from Hybrid Neuro-Symbolic Systems.	IJCNN	2006	DBLP DOI BibTeX RDF