Search results for "parametric yield"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester	Parametric yield estimation considering leakage variability.	DAC	2004	DBLP DOI BibTeX RDF	variability, leakage, parametric yield
2	Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu	Transistor sizing of custom high-performance digital circuits with parametric yield considerations.	DAC	2010	DBLP DOI BibTeX RDF	custom circuits, optimization
2	Fang Gong, Hao Yu, Yiyu Shi, Daesoo Kim, Junyan Ren, Lei He	QuickYield: an efficient global-search based parametric yield estimation with performance constraints.	DAC	2010	DBLP DOI BibTeX RDF	circuit simulation, parametric yield
2	Cesare Ferri, Sherief Reda, R. Iris Bahar	Parametric yield management for 3D ICs: Models and strategies for improvement.	JETC	2008	DBLP DOI BibTeX RDF	performance, process variations, leakage, 3D integration, yield management
2	Jin Sun, Jun Li, Dongsheng Ma, Janet Meiling Wang	Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Xin Li, Yaping Zhan, Lawrence T. Pileggi	Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Jin Sun, Yue Huang, Jun Li, Janet Meiling Wang	Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan	A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Ming-e Jing, Yue Hao, Dian Zhou, Xuan Zeng	A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown	Parametric Yield Analysis and Optimization in Leakage Dominated Technologies.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Ayhan A. Mutlu, Kelvin J. Le, Mustafa Celik, Dar-sun Tsien, Garry Shyu, Long-Ching Yeh	An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
2	Shubhankar Basu, Ranga Vemuri	Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Xin Li, Lawrence T. Pileggi	Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits.	DAC	2007	DBLP DOI BibTeX RDF
2	Cesare Ferri, Sherief Reda, R. Iris Bahar	Strategies for improving the parametric yield and profits of 3D ICs.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah	Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Wei-Shen Wang, Michael Orshansky	Robust estimation of parametric yield under limited descriptions of uncertainty.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Murari Mani, Ashish Kumar Singh, Michael Orshansky	Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Antonis Papanikolaou, T. Grabner, Miguel Miranda, Philippe Roussel, Francky Catthoor	Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	system exploration, process variability, parametric yield
2	Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan	Modeling and Analysis of Parametric Yield under Power and Performance Constraints.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	G.4.g Reliability and robustness, B.7 Integrated Circuits, Fault-Tolerance
2	Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown	Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization.	ISQED	2005	DBLP DOI BibTeX RDF
2	Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director	Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.	DAC	2005	DBLP DOI BibTeX RDF	correlation, variability, yield, leakage
2	Antonis Papanikolaou, F. Lobmaier, Hua Wang, Miguel Miranda, Francky Catthoor	A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	system-level compensation, process variability, parametric yield
2	Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown	Optimization objectives and models of variation for statistical gate sizing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	parametric yield optimization, robust design
2	Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah	Statistical timing for parametric yield prediction of digital integrated circuits.	DAC	2003	DBLP DOI BibTeX RDF	statistical timing, yield prediction
2	Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti	Parametric yield formulation of MOS IC's affected by mismatch effect.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
2	Ting Wu, Say Wei Foo	An efficient method for parametric yield gradient estimation.	ISCAS	1999	DBLP DOI BibTeX RDF
2	G. S. Samudra, H. M. Chen, D. S. H. Chan, Yaacob Ibrahim	Yield Optimization by Design Centering and Worst-Case Distance Analysis.	ICCD	1999	DBLP DOI BibTeX RDF	worst-case distance, design centering, optimization, VLSI design, parametric yield
2	Kanji Hirabayashi	A parametric yield model.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	AC yield, delay defect, exponential distribution
2	Dale E. Hocevar, Paul F. Cox, Ping Yang	Parametric yield optimization for MOS circuit blocks.	IEEE Trans. on CAD of Integrated Circuits and Systems	1988	DBLP DOI BibTeX RDF
1	Siddharth Garg, Diana Marculescu	Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutions.	VTS	2011	DBLP DOI BibTeX RDF
1	R. Aitken, Greg Yeric, D. Flynn	Correlating models and silicon for improved parametric yield.	DATE	2011	DBLP BibTeX RDF
1	Sudip Roy, Ajit Pal	A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas	Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology.	Microelectronics Reliability	2010	DBLP DOI BibTeX RDF
1	Yibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach	Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Cheng Zhuo, Yung-Hsu Chang, Dennis Sylvester, David Blaauw	Design time body bias selection for parametric yield improvement.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Paul Zuber, Petr Dobrovolný, Miguel Miranda	A holistic approach for statistical SRAM analysis.	DAC	2010	DBLP DOI BibTeX RDF	statistical SRAM analysis, process variability, yield prediction
1	Mark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels	DFM: don't care or competitive weapon?	DAC	2009	DBLP DOI BibTeX RDF	RDR, physical verification, sign-off, yield, DFM, design-for-manufacturing, design rules, manufacturing variability, DRC
1	Amlan Ghosh, Rahul M. Rao, Richard B. Brown	A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation.	ISLPED	2009	DBLP DOI BibTeX RDF	fine-grain body-biasing, process variation compensation, slewrate
1	Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li	Tolerating process variations in large, set-associative caches: The buddy cache.	TACO	2009	DBLP DOI BibTeX RDF	caches, Processor architectures, fault recovery, memory structures
1	Hailong You, Maofeng Yang, Dan Wang, Xinzhang Jia	Kriging Model combined with latin hypercube sampling for surrogate modeling of analog integrated circuit performance.	ISQED	2009	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	N. Pete Sedcole, Peter Y. K. Cheung	Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations.	TRETS	2008	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modeling, FPGA, Delay, reconfiguration, process variation, yield
1	Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor	Combining system scenarios and configurable memories to tolerate unpredictability.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	variability compensation, Process variation, parametric yield
1	Andrew B. Kahng	How to get real mad.	ISPD	2008	DBLP DOI BibTeX RDF	design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability
1	Chenjie Gu, Jaijeet S. Roychowdhury	An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Brendan Hargreaves, Henrik Hult, Sherief Reda	Within-die process variations: How accurately can they be statistically modeled?	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Sridhar Varadan, Janet Meiling Wang, Jiang Hu	Handling partial correlations in yield prediction.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Xiaoxia Wu, Yuan Xie	Variability-driven module selection with joint design time optimization and post-silicon tuning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Guangyu Sun, Yuan Xie	A Variation Aware High Level Synthesis Framework.	DATE	2008	DBLP DOI BibTeX RDF
1	Sudip Roy, Ajit Pal	Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?	DSD	2008	DBLP DOI BibTeX RDF
1	Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown	On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.	ISQED	2008	DBLP DOI BibTeX RDF
1	Lin Xie, Azadeh Davoodi	Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations.	ISQED	2008	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Kaushik Roy	Low power design under parameter variations.	SoCC	2008	DBLP DOI BibTeX RDF
1	Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown	On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Kian Haghdad, Mohab Anis	Design-Specific Optimization Considering Supply and Threshold Voltage Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Chul-Hong Park, Xu Xu	Fast Dual-Graph-Based Hotspot Filtering.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Kambiz Samadi	CMP Fill Synthesis: A Survey of Recent Studies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy	Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw	A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Lin Xie, Azadeh Davoodi	Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Wei-Shen Wang, Michael Orshansky	Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters.	J. Low Power Electronics	2007	DBLP DOI BibTeX RDF
1	Shyam Praveen Vudathu, Kishore K. Duganapalli, Rainer Laur, D. Kubalinska, Angelika Bunse-Gerstner	Parametric Yield Analysis of Mems via Statistical Methods	CoRR	2007	DBLP BibTeX RDF
1	N. Pete Sedcole, Peter Y. K. Cheung	Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.	FPGA	2007	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield
1	Shiyan Hu, Jiang Hu	Unified adaptivity optimization of clock and logic signals.	ICCAD	2007	DBLP DOI BibTeX RDF	clock signal tuning, logic signal tuning, post-silicon tuning, robustness, variation
1	Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	booster circuit, low power, yield, SRAM
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
1	Kunhyuk Kang, Keejong Kim, Kaushik Roy	Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop.	DAC	2007	DBLP DOI BibTeX RDF
1	Guo Yu, Wei Dong, Zhuo Feng, Peng Li	A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis.	DAC	2007	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy	Tolerance to Small Delay Defects by Adaptive Clock Stretching.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Shubhankar Basu, Priyanka Thakore, Ranga Vemuri	Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques.	ISQED	2007	DBLP DOI BibTeX RDF
1	Amith Singhee, Rob A. Rutenbar	From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis.	ISQED	2007	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy	Process Variations and Process-Tolerant Design.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy, Muhammad Ashraful Alam	Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh	SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Saumil Shah, Puneet Gupta, Andrew B. Kahng	Standard cell library optimization for leakage reduction.	DAC	2006	DBLP DOI BibTeX RDF	gate-length biasing, library optimization, leakage reduction
1	Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, R. Sommer, Michael Pronath, Andreas Ripp	DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.	DATE	2006	DBLP DOI BibTeX RDF
1	Alberto Fazzi, L. Magagni, Mario de Dominicis, Paolo Zoffoli, Roberto Canegallo, Pier Luigi Rolandi, Alberto L. Sangiovanni-Vincentelli, Roberto Guerrieri	Yield prediction for 3D capacitive interconnections.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky	Fill for shallow trench isolation CMP.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Lukasz Zielinski, Bartlomiej Puchalski, Jerzy Rutkowski	Yield enhancement by means of evolutionary computation techniques.	ISCAS	2006	DBLP DOI BibTeX RDF
1	S. Tirumala, Y. Mahotin, Xiao Lin, Victor Moroz, Lee Smith, S. Krishnamurthy, L. Bomholt, Dipu Pramanik	Bringing Manufacturing into Design via Process-Dependent SPICE Models.	ISQED	2006	DBLP DOI BibTeX RDF
1	Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou	Yield-Aware Cache Architectures.	MICRO	2006	DBLP DOI BibTeX RDF
1	Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester	Analytical yield prediction considering leakage/performance correlation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta	Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Ming-e Jing, Yue Hao, JinFeng Zhang, Peijun Ma	Efficient parametric yield optimization of VLSI circuit by uniform design sampling method.	Microelectronics Reliability	2005	DBLP DOI BibTeX RDF
1	Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester	Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.	ICCAD	2005	DBLP BibTeX RDF
1	Ashish Kumar Singh, Murari Mani, Michael Orshansky	Statistical technology mapping for parametric yield.	ICCAD	2005	DBLP BibTeX RDF
1	David Blaauw, Kaviraj Chopra	CAD tools for variation tolerance.	DAC	2005	DBLP DOI BibTeX RDF	variability, yield, design flows
1	Murari Mani, Anirudh Devgan, Michael Orshansky	An efficient algorithm for statistical minimization of total power under timing yield constraints.	DAC	2005	DBLP DOI BibTeX RDF	manufacturability, leakage, statistical optimization
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd	A New Method for Design of Robust Digital Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
1	Rajesh K. Gupta	Nanotechnology: Where science of the small meets math of the large.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	scalability, integration, reconfiguration, nanotechnology, defect tolerance
1	Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang 0010	Toward a methodology for manufacturability-driven design rule exploration.	DAC	2004	DBLP DOI BibTeX RDF	VLSI manufacturability, process variation, yield, OPC, lithography, RET
1	Farid N. Najm, Noel Menezes	Statistical timing analysis based on a timing yield model.	DAC	2004	DBLP DOI BibTeX RDF	statistical timing analysis, principal components, timing yield
1	Chandu Visweswariah	Death, taxes and failing chips.	DAC	2003	DBLP DOI BibTeX RDF	parametric yield prediction, design methodology, Statistical timing
1	Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang 0010	A cost-driven lithographic correction methodology based on off-the-shelf sizing tools.	DAC	2003	DBLP DOI BibTeX RDF	VLSI manufacturability, yield, OPC, lithography, RET
1	Juin J. Liou, Qiang Zhang, John McMacken, J. Ross Thomson, Kevin Stiles, Paul Layman	Statistical modeling of MOS devices for parametric yield prediction.	Microelectronics Reliability	2002	DBLP DOI BibTeX RDF
1	Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb	Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets.	DATE	2002	DBLP DOI BibTeX RDF
1	Madhuban Kishor, José Pineda de Gyvez	Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. (PDF / PS)	DFT	2000	DBLP DOI BibTeX RDF