Search results for "performance design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Shinichi Honiden, Kazuhiko Nishimura, Naoshi Uchihira, Kiyoshi Itoh	An Application of Artificial Intelligence to Object-Oriented Performance Design for Real-Time Systems.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	object-oriented performance design, rapid prototyping method, OOPD, prototyping phases, prototype construction, prototype execution, artificial intelligence based methods, rapid construction mechanism, hybrid inference mechanism, declarative knowledge representation, MENDEL, Prolog based concurrent object-oriented language, prototype construction tool, real-time systems, real-time systems, artificial intelligence, object-oriented programming, knowledge representation, expert systems, expert system, software reusability, inference mechanisms, object-oriented languages, parallel languages, software prototyping, qualitative reasoning, reusable software components, prototype evaluation
2	H. K. Lam, Lakmal D. Seneviratne	BMI-Based Stability and Performance Design for Fuzzy-Model-Based Control Systems Subject to Parameter Uncertainties.	IEEE Transactions on Systems, Man, and Cybernetics, Part B	2007	DBLP DOI BibTeX RDF
2	Joonsoo Kim, Michael Orshansky	Towards formal probabilistic power-performance design space exploration.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	formal methodology, hierarchical design exploration, performance, power, probabilistic, canonical representation
2	Ravishankar Rao, Mark Oskin, Frederic T. Chong	HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space.	HiPC	2002	DBLP DOI BibTeX RDF
2	Michael Benoit, Sandy Taylor, David Overhauser, Steffen Rochel	Power distribution in high-performance design.	ISLPED	1998	DBLP DOI BibTeX RDF	power grid, IR drop, power distribution
1	Kenjiro Yamanaka	Clock driven programming: a programming paradigm which enables machine-independent performance design.	ICPE	2012	DBLP DOI BibTeX RDF
1	Mohammad Javad Sharifi, Davoud Bahrepour	Introducing a technology index concept and optimum performance design procedure for single-electron-device based circuits.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	S. M. Stalin, Amit Brahme, Ramakrishnan Venkatraman, Ajoy Mandal	DFM: Impact analysis in a high performance design.	ISQED	2011	DBLP DOI BibTeX RDF
1	Ismail Saad, Nurmin Bolong, P. Divya, Kenneth Tze Kin Teo	Performance Design and Simulation Analysis of Vertical Double Gate MOSFET (VDGM).	UKSim	2011	DBLP DOI BibTeX RDF
1	Tzu-Sung Wu, Wen-Shyong Yu	Delayed-based H INFINITY tracking performance design for chaotic systems.	SMC	2010	DBLP DOI BibTeX RDF
1	Arpad Gellert, Gianluca Palermo, Vittorio Zaccaria, Adrian Florea, Lucian N. Vintan, Cristina Silvano	Energy-performance design space exploration in SMT architectures exploiting selective load value predictions.	DATE	2010	DBLP BibTeX RDF
1	Miao Luo, Sreeram Potluri, Ping Lai, Emilio Pasquale Mancini, Hari Subramoni, Krishna Chaitanya Kandalla, Sayantan Sur, Dhabaleswar K. Panda	High Performance Design and Implementation of Nemesis Communication Layer for Two-Sided and One-Sided MPI Semantics in MVAPICH2.	ICPP Workshops	2010	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs)
1	Wen-Shyong Yu	H∞ Tracking Performance Design for Fuzzy-Model-Based Descriptor Systems Subject to Parameter Uncertainties.	JCP	2009	DBLP DOI BibTeX RDF
1	Hak-Keung Lam, Mohammad Narimani	Stability Analysis and Performance Design for Fuzzy-Model-Based Control System Under Imperfect Premise Matching.	IEEE T. Fuzzy Systems	2009	DBLP DOI BibTeX RDF
1	Haoxing Ren, Mary P. Kusko, Victor N. Kravets, Rona Yaari	Low cost test point insertion without using extra registers for high performance design.	ITC	2009	DBLP DOI BibTeX RDF
1	Norman P. Jouppi, Yuan Xie	Emerging technologies and their impact on system design.	ISLPED	2009	DBLP DOI BibTeX RDF	new non-volatile memory technology, emerging technology, 3d integration
1	Duo Ding, David Z. Pan	OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture.	SLIP	2009	DBLP DOI BibTeX RDF	photonic networks-on-chip, low power, computer aided design, high performance
1	Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	Efficient partial scan cell gating for low-power scan-based testing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	partial gating, scan cell gating, Low-power testing, scan-based testing
1	Ching-Wen Chen, Chun-Liang Lai	An improved efficient performance design with multiple channels and bandwidth allocation strategy for mobile ad hoc networks.	Int. J. Pervasive Computing and Communications	2008	DBLP DOI BibTeX RDF
1	Shuai Wang, Jie S. Hu, Sotirios G. Ziavras	BTB Access Filtering: A Low Energy and High Performance Design.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli	Programmable logic circuits based on ambipolar CNFET.	DAC	2008	DBLP DOI BibTeX RDF	CNFET, FPGA, PLA, carbon nanotube
1	Morteza Damavandpeyma, Siamak Mohammadi	Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool.	DSD	2008	DBLP DOI BibTeX RDF
1	Ling Zhuo, Viktor K. Prasanna	High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Xiaoqing Cheng	Performance, Benchmarking and Sizing in Developing Highly Scalable Enterprise Software.	SIPEW	2008	DBLP DOI BibTeX RDF
1	Jennifer Gluck, Andrea Bunt, Joanna McGrenere	Matching attentional draw with utility in interruption.	CHI	2007	DBLP DOI BibTeX RDF	annoyance, attention, detection, interruption, utility, benefit, mental workload
1	Yazhuo Dong, Yong Dou	A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Hak-Keung Lam, Chun Wan Yeung, F. H. Frank Leung	Stability Analysis and Performance Deign for Fuzzy-Model-Based Control System under Imperfect Premise Matching.	FUZZ-IEEE	2007	DBLP DOI BibTeX RDF
1	Savvas Koudounas, Julius Georgiou	A Reduced-Area, Low-Power CMOS Bandgap Reference Circuit.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Andre Silva, Guilherme Esmeraldo, Edna Barros, Pablo Viana	Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Michael J. Johnson, Chih-Wei Ho, E. Michael Maximilien, Laurie Williams	Incorporating Performance Testing in Test-Driven Development.	IEEE Software	2007	DBLP DOI BibTeX RDF	performance measures, testing strategies, test execution
1	Jun Chen, Lei He	Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	H. K. Lam, F. H. Frank Leung	LMI-Based Stability and Performance Conditions for Continuous-Time Nonlinear Systems in Takagi-Sugeno's Form.	IEEE Transactions on Systems, Man, and Cybernetics, Part B	2007	DBLP DOI BibTeX RDF
1	H. K. Lam, F. H. Frank Leung	Sampled-Data Fuzzy Controller for Time-Delay Nonlinear Systems: Fuzzy-Model-Based LMI Approach.	IEEE Transactions on Systems, Man, and Cybernetics, Part B	2007	DBLP DOI BibTeX RDF
1	Ming Xiao, Tor Aulin	On Analysis and Design of Low Density Generator Matrix Codes for Continuous Phase Modulation.	IEEE Transactions on Wireless Communications	2007	DBLP DOI BibTeX RDF
1	Mini Nanua, David Blaauw	Crosstalk Waveform Modeling Using Wave Fitting.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Hong Yue, Aurelie J. A. Leprand, Hong Wang 0001	Output PDF Shaping of Singular Weights System: Monotonical Performance Design.	ISNN	2006	DBLP DOI BibTeX RDF
1	Ching-Wen Chen, Chun-Liang Lai	An Improved Efficient Performance Design with Multiple Channels and Bandwidth Allocation Strategy for Mobile Ad-Hoc Networks.	SUTC	2006	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	System-level power-performance trade-offs in bus matrix communication architecture synthesis.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs
1	Hao Hua, Christopher Mineo, Kory Schoenfliess, Ambarish M. Sule, Samson Melamed, Ravi Jenkal, W. Rhett Davis	Exploring compromises among timing, power and temperature in three-dimensional integrated circuits.	DAC	2006	DBLP DOI BibTeX RDF	trade off, design flow, temperature dependency, 3DIC
1	Sayantan Sur, Matthew J. Koop, Dhabaleswar K. Panda	MPI and communication - High-performance and scalable MPI over InfiniBand with reduced memory usage: an in-depth performance analysis.	SC	2006	DBLP DOI BibTeX RDF
1	Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede	Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip.	ASAP	2006	DBLP DOI BibTeX RDF
1	Haiqian Yu, Miriam Leeser	Automatic Sliding Window Operation Optimization for FPGA-Based.	FCCM	2006	DBLP DOI BibTeX RDF
1	Ling Zhuo, Viktor K. Prasanna	High-Performance and Parameterized Matrix Factorization on FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
1	Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh	Power minimization for dynamic PLAs.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Fabio Wronski, Eduardo Wenzel Brião, Flávio Rech Wagner	Evaluating Energy-Aware Task Allocation Strategies for MPSOCS.	DIPES	2006	DBLP DOI BibTeX RDF	Simulation, Networks-on-Chip, Task Allocation, Multiprocessor SoCs, Energy Estimation
1	James Tschanz, Keith A. Bowman, Vivek De	Variation-tolerant circuits: circuit solutions and techniques.	DAC	2005	DBLP DOI BibTeX RDF	parameter variation, body bias, high-performance design
1	Hüseyin Kuscu, B. Tevfik Akgün	A new approach to interactive performance systems.	ACM Multimedia	2005	DBLP DOI BibTeX RDF	dance and multimedia, dance technology, interaction composition, performance design, virtual performance, virtual environment, choreography, interactive performance
1	Rob Roy, Debashis Bhattacharya, Vamsi Boppana	Transistor-Level Optimization of Digital Designs with Flex Cells.	IEEE Computer	2005	DBLP DOI BibTeX RDF	ASIC design methodology, integrated circuit design, power optimization, design and test, high-performance design
1	Zhijun Huang, Milos D. Ercegovac	High-Performance Low-Power Left-to-Right Array Multiplier Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Left-to-right array multiplier, tree multiplier, layout regularity, low-power design, high-performance design
1	Xiao Yong, Zhou Runde	Single-track asynchronous pipeline controller design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Ruchir Puri, Leon Stok, Subhrajit Bhattacharya	Keeping hot chips cool.	DAC	2005	DBLP DOI BibTeX RDF	low power, high-performance, VLSI design
1	Melvin A. Breuer	Multi-media Applications and Imprecise Computation.	DSD	2005	DBLP DOI BibTeX RDF
1	Dheeraj Bhardwaj, Rishi Kumar	A Parallel File Transfer Protocol for Clusters and Grid Systems.	e-Science	2005	DBLP DOI BibTeX RDF
1	Chao Li, Lizhu Zhou, Chunxiao Xing	Using MMQ Model for Performance Simulation of Storage Area Network.	ICDE Workshops	2005	DBLP DOI BibTeX RDF
1	Michael Van Wie, Robert B. Stone, Asli Sahin, Janis P. Terpenny, Fabrice Alizon, Steven B. Shooter, Timothy W. Simpson	A qualitative modeling method for platform design.	IRI	2005	DBLP DOI BibTeX RDF
1	Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova	Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.	MTV	2005	DBLP DOI BibTeX RDF
1	Heiko Koziolek, Viktoria Firus	Empirical Evaluation of Model-Based Performance Prediction Methods in Software Development.	QoSA/SOQUA	2005	DBLP DOI BibTeX RDF
1	Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham	On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.	ITC	2004	DBLP DOI BibTeX RDF
1	Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham	On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.	MTV	2004	DBLP DOI BibTeX RDF
1	Jiuxing Liu, Weihang Jiang, Pete Wyckoff, Dhabaleswar K. Panda, David Ashton, Darius Buntinas, William D. Gropp, Brian R. Toonen	Design and Implementation of MPICH2 over InfiniBand with RDMA Support.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He	Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.	ISQED	2004	DBLP DOI BibTeX RDF
1	Victor H. S. Ha, Sung Kyu Choi, Jong-Gu Jeon, Geon Hyoung Lee, Won-Kap Jang, Woo-Sung Shim	Real-time Audio/Video Decoders for Digital Multimedia Broadcasting.	IWSOC	2004	DBLP DOI BibTeX RDF
1	Jeong-Gun Lee, Euiseok Kim, Jeong-A. Lee, Eunok Paek	Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
1	James Northern III, Michael A. Shanblatt	A Multi-objective Approach to Configuring Embedded System Architectures.	GECCO	2004	DBLP DOI BibTeX RDF
1	Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre	Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Shamik Das, Anantha Chandrakasan, Rafael Reif	Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Yu Chen, Zhenqiang Jiao, Jun Xie, Zhihui Du, Peng Liu, Ziyu Zhu	A High Performance Design and Implementation of the Virtual Interface Architecture.	APPT	2003	DBLP DOI BibTeX RDF
1	Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas	Layered, Multi-Threaded, High-Level Performance Design.	DATE	2003	DBLP DOI BibTeX RDF
1	Ted Vucurevich	Advanced EDA Tools for High-Performance Design. (PDF / PS)	ICCD	2003	DBLP DOI BibTeX RDF
1	Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen	Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction.	MICRO	2003	DBLP DOI BibTeX RDF
1	Anand Selvarathinam, Euncheol Kim, Gwan Choi	Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels.	ICCD	2003	DBLP DOI BibTeX RDF	LDPC Decoder, Serial Architecture, Hardware Scaling, VLSI, Parallel Architecture, Fibre Channel
1	J. Shorb, Xiaoyong Li, David J. Allstot	A resonant pad for ESD protected narrowband CMOS RF applications.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris	Extraction Error Diagnosis and Correction in High-Performance Designs.	ITC	2003	DBLP DOI BibTeX RDF
1	Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir	A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits.	MTV	2003	DBLP DOI BibTeX RDF
1	Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris	Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs.	MTV	2003	DBLP DOI BibTeX RDF
1	Alexandre F. Tenca, Çetin Kaya Koç	A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	modular multiplier, scalable multiplier, Cryptography, Montgomery multiplication, modular multiplication
1	K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz	Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations.	FPL	2003	DBLP DOI BibTeX RDF
1	Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Prashant Saxena, Satyanarayan Gupta	Shield count minimization in congested regions.	ISPD	2002	DBLP DOI BibTeX RDF	power routing, routing, noise, layout, crosstalk, shielding, high performance design, domino circuits
1	Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac	High-Level Synthesis with SIMD Units.	VLSI Design	2002	DBLP DOI BibTeX RDF	SIMD functional units, High-level synthesis, high performance design
1	Felix T. S. Chan	Comparative evaluation of supply chain management strategies: a simulation approach.	ICARCV	2002	DBLP DOI BibTeX RDF
1	Ertan Zencir, Numan Sadi Dogan, Ercument Arvas	A 10-mW 435-MHz differential CMOS LNA for low-IF receivers in space applications.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Tony Givargis, Frank Vahid, Jörg Henkel	System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Mohammad Reza Sirouspour, S. E. Salcudean	Robust Controller Design for Cancelling Biodynamic Feedthrough.	ISER	2002	DBLP DOI BibTeX RDF
1	Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia	Buffered Steiner trees for difficult instances.	ISPD	2001	DBLP DOI BibTeX RDF
1	Kenneth Y. Jo	Satellite communications representation in network simulation.	Winter Simulation Conference	2001	DBLP DOI BibTeX RDF
1	Vikram S. Adve, Rajive Bagrodia, James C. Browne, Ewa Deelman, Aditya Dube, Elias N. Houstis, John R. Rice, Rizos Sakellariou, David Sundaram-Stukel, Patricia J. Teller, Mary K. Vernon	POEMS: End-to-End Performance Design of Large Parallel Adaptive Computational Systems.	IEEE Trans. Software Eng.	2000	DBLP DOI BibTeX RDF	recommender system, message passing, Performance modeling, analytical modeling, parallelizing compiler, parallel system, parallel simulation, task graph, compositional modeling, processor simulation
1	Vivek De, Shekhar Borkar	Low power and high performance design challenges in future technologies.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	low-power design, memory, microprocessor, VLSI design
1	Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas	Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
1	Jason Cong, Xin Yuan	Routing tree construction under fixed buffer locations.	DAC	2000	DBLP DOI BibTeX RDF
1	Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov	ClariNet: a noise analysis tool for deep submicron design.	DAC	2000	DBLP DOI BibTeX RDF
1	José Luis Neves, Stephen T. Quay	Buffer Library Selection. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Weidong Zhang, Xiaoming Xu, Youxian Sun	Quantitative performance design for integrating processes with time delay.	Automatica	1999	DBLP DOI BibTeX RDF
1	Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking	A Robust Solution to the Timing Convergence Problem in High-Performance Design.	ICCD	1999	DBLP DOI BibTeX RDF	timing convergence, maximum capacitance, synthesis, placement, design-rules
1	Thomas A. Cwik, Gerhard Klimeck	Genetically Engineered Microelectronic Infrared Filters.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Wei Hwang	Design Considerations and Implementation of a High Performance Dynamic Register File.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Buffer insertion for noise and delay optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng	Sequence-pair approach for rectilinear module placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Ewa Deelman, Aditya Dube, Adolfy Hoisie, Yong Luo, Richard L. Oliver, David Sundaram-Stukel, Harvey J. Wasserman, Vikram S. Adve, Rajive Bagrodia, James C. Browne, Elias N. Houstis, Olaf M. Lubeck, John R. Rice, Patricia J. Teller, Mary K. Vernon	Poems: end-to-end performance design of large parallel adaptive computational systems.	WOSP	1998	DBLP DOI BibTeX RDF