Search results for "performance growth"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Magnus Ekman, Fredrik Warg, Jim Nilsson	An in-depth look at computer performance growth.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
2	David Parry	Scalability in computing for today and tomorrow.	ARVLSI	1997	DBLP DOI BibTeX RDF	synergistic combination, performance growth, current multiprocessor alternatives, scalable SMP, Silicon Graphics Origin multiprocessor, S/sup 2/MP memory architecture, core technologies, scalability, system architecture, shared-memory multiprocessors, shared memory systems
1	Raj R. Nadakuditi, Igor L. Markov	On the costs and benefits of stochasticity in stream processing.	DAC	2010	DBLP DOI BibTeX RDF	latency, stochasticity, stream computing
1	Xiaochen Guo, Engin Ipek, Tolga Soyata	Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing.	ISCA	2010	DBLP DOI BibTeX RDF	STT-MRAM, power-efficiency
1	Joseph M. Hellerstein	Datalog redux: experience and conjecture.	PODS	2010	DBLP DOI BibTeX RDF	bloom, boom, dedalus, overlog, distributed systems, parallelism, cloud computing, datalog
1	Yao Qi, Raja Das, Zhi Da Luo, Martin Trotter	MulticoreSDK: a practical and efficient data race detector for real-world applications.	PADTAD	2009	DBLP DOI BibTeX RDF	concurrent program analysis, multicore platform, data race detection
1	Yifang Liu, Jiang Hu, Weiping Shi	Multi-scenario buffer insertion in multi-core processor designs.	ISPD	2008	DBLP DOI BibTeX RDF	multi-core design, buffer insertion
1	Martin Palkovic, Hans Cappelle, Miguel Glassee, Bruno Bougard, Liesbet Van der Perre	Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform.	DDECS	2008	DBLP DOI BibTeX RDF
1	Yifang Liu, Jiang Hu, Weiping Shi	Buffering Interconnect for Multicore Processor Designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Cor Meenderinck, Ben H. H. Juurlink	(When) Will CMPs Hit the Power Wall?.	Euro-Par Workshops	2008	DBLP DOI BibTeX RDF
1	Avi Mendelson	Current trends in computer architectures: multi-cores, many-cores and special-cores.	ICS	2007	DBLP DOI BibTeX RDF
1	Kerry Bernstein, Paul Andry, Jerome Cann, Philip G. Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steven J. Koester, John Magerlein, Ruchir Puri, Albert M. Young	Interconnects in the Third Dimension: Design Challenges for 3D ICs.	DAC	2007	DBLP DOI BibTeX RDF
1	Uzi Vishkin	Toward Realizing a PRAM-on-a-Chip Vision.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
1	Wei Qin, Joseph D'Errico, Xinping Zhu	A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	retargetable, instruction set simulator, compiled simulation
1	Wesley M. Felter, Karthick Rajamani, Tom W. Keller, Cosmin Rusu	A performance-conserving approach for reducing peak power consumption in server systems.	ICS	2005	DBLP DOI BibTeX RDF	power management, power modeling, processor simulation
1	Pradip Bose	Integrated microarchitectures.	IEEE Micro	2005	DBLP DOI BibTeX RDF
1	Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger	Clock rate versus IPC: the end of the road for conventional microarchitectures.	ISCA	2000	DBLP DOI BibTeX RDF
1	Kai Hwang, Zhiwei Xu, Masahiro Arakawa	Benchmark Evaluation of the IBM SP2 for Parallel Signal Processing.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	adaptive sensor array processing, STAP benchmarks, performance evaluation, scalability, Message passing, real-time applications, data parallelism, programmability, massively parallel processors