Search results for "pipeline"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Hans M. Jacobson	Improved clock-gating through transparent pipelining.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating
6	Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even	Pipelined Packet-Forwarding Floating Point: II. An Adder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, floating point addition algorithm, adder pipeline design, packet forwarding pipeline paradigm, data hazards, deeply pipelined floating point pipelines, four stage execution phase pipeline, short clock period, fifteen logic levels, addition algorithm, standard binary floating point format, standard IEEE 754 rounded result, two cycle latency, cooperating multiplier pipeline, packet forwarding operand, IEEE 754 binary floating point compatibility, pipeline arithmetic
5	Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu	ARAS: asynchronous RISC architecture simulator.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing
4	Kenneth Eguro, Scott Hauck	Armada: timing-driven pipeline-aware routing for FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	pipeline FPGA, pipeline routing, reconfigurable computing
4	Prabhat Mishra, Nikil Dutt	Modeling and validation of pipeline specifications.	ACM Trans. Embedded Comput. Syst.	2004	DBLP DOI BibTeX RDF	Modeling of processor pipeline, pipeline validation, pipelined processor specification, architecture description language
4	Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg	A case for dynamic pipeline scaling.	CASES	2002	DBLP DOI BibTeX RDF	configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating
4	Masayuki Tsukisaka, Takashi Nanya	A testable design for asynchronous fine-grain pipeline circuits.	PRDC	2000	DBLP DOI BibTeX RDF	asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
4	Hai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha	Improving self-timed pipeline ring performance through the addition of buffer loops.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	buffer circuits, self-timed pipeline ring performance, buffer loops, communication scheme, communication delay reduction, data communication delay, pace handshaking overhead, initial system configuration, performance evaluation, delays, timing, logic design, asynchronous circuits, pipeline processing
4	Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov	Designing an asynchronous pipeline token ring interface.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous pipeline token ring interface, speed-independent interface, reliable communication medium, on-board multicomputer, asynchronous buses, point-to-point interconnections, syntax-driven implementation, channel protocol controller, protocols, fairness, multiprocessor interconnection networks, local area networks, pipeline processing, deadlock-freedom, token networks
4	Prathima Agrawal, Antony Ng	Computing Network Flow on a Multiple Processor Pipeline.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	multiple processor pipeline, Goldberg-Tarjan algorithm, network graph, six processors, distributed algorithms, graph theory, network flow, pipeline processing, parallel implementations, performance estimates, maximum flow, partitioned algorithm, message-passing multicomputer
4	Arthur Abnous, Nader Bagherzadeh	Pipelining and Bypassing in a VLIW Processor.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	VLIWprocessor, very long instruction word, pipeline data hazards, performance evaluation, performance, parallel architectures, computer architecture, pipeline processing, pipeline structure, bypassing
3	Sherif Ghali	Sense and sidedness in the graphics pipeline via a passage through a separable space.	The Visual Computer	2009	DBLP DOI BibTeX RDF	Oriented projective geometry, Separability, Projective geometry, Homogeneous coordinates, Graphics pipeline
3	Kuan-Wei Cheng, Tzong-Yen Lin, Rong-Guey Chang	Profile-based dynamic pipeline scaling.	The Journal of Supercomputing	2009	DBLP DOI BibTeX RDF	DPS, Pipeline mode, Loop region, DVS, IPC
3	Wu Liu, Min Li, Yi Liu, Yuan Xu, Xinglan Yang	Decision of optimal scheduling scheme for gas field pipeline network based on hybrid genetic algorithm.	GEC Summit	2009	DBLP DOI BibTeX RDF	natural gas pipeline network, genetic algorithm, optimization, scheduling scheme, differential evolution algorithm
3	MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada	Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dcvsl, high speed digital, pipeline, error detect, soft error
3	L. I. Zhen-pei, L. I. Ping, W. U. Ming	Digital oil and gas pipeline visualization using X3D.	Web3D	2009	DBLP DOI BibTeX RDF	Java native interface (JNI), OLE for process control (OPC), digital oil and gas pipeline, scene access interface (SAI), visualization, interaction, 3D modeling, extensible 3D (X3D)
3	Angeles G. Navarro, Rafael Asenjo, Siham Tabik, Calin Cascaval	Load balancing using work-stealing for pipeline parallelism in emerging applications.	ICS	2009	DBLP DOI BibTeX RDF	work-stealing, load imbalance, parallel pipeline
3	A. Folorunso Olufemi, Mohd Shahrizal Sunar, Sarudin Kari	An Algorithm for Treating Uncertainties in the Visualization of Pipeline Sensors' Datasets.	IVIC	2009	DBLP DOI BibTeX RDF	Uncertainty Visualisation, Nuggets, Pipeline-Sensors, Signal Dataspace, LDS
3	Jarkko Ylipaavalniemi, Jyri Soppela	Arabica: Robust ICA in a Pipeline.	ICA	2009	DBLP DOI BibTeX RDF	pipeline, ICA, bootstrapping, fMRI, Toolbox
3	Amy Bruckman, Maureen Biggers, Barbara Ericson, Tom McKlin, Jill P. Dimond, Betsy James DiSalvo, Mike Hewner, Lijun Ni, Sarita Yardi	"Georgia computes!": improving the computing education pipeline.	SIGCSE	2009	DBLP DOI BibTeX RDF	computing education pipeline, summer camps, introductory courses
3	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith	A mechanistic performance model for superscalar out-of-order processors.	ACM Trans. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling
3	Álvaro García-Sánchez, Luis Miguel Arreche Bedia, Miguel Ortega-Mier	Combining Simulation and Tabu Search for Oil-derivatives Pipeline Scheduling.	Metaheuristics for Scheduling in Industrial and Manufacturing Applications	2008	DBLP DOI BibTeX RDF	Multi-commodity Pipeline, Real World Instances, Simulation, Scheduling, Tabu Search
3	Nary Subramanian	Improving Security of Oil Pipeline SCADA Systems Using Service-Oriented Architectures.	OTM Workshops	2008	DBLP DOI BibTeX RDF	petroleum, security, architecture, pipeline, services, SCADA
3	Anne Benoit, Harald Kosch, Veronika Rehn-Sonigo, Yves Robert	Bi-criteria Pipeline Mappings for Parallel Image Processing.	ICCS	2008	DBLP DOI BibTeX RDF	workflow application, JPEG encoding, optimization, pipeline, multi-criteria
3	Raghid Shreih, Maitham Shams	Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	c-element, gasp, low power, pipeline, asynchronous, multi-threshold
3	Allan MacKenzie-Graham, Arash Payan, Ivo D. Dinov, John D. Van Horn, Arthur W. Toga	Neuroimaging Data Provenance Using the LONI Pipeline Workflow Environment.	IPAW	2008	DBLP DOI BibTeX RDF	Grid, Workflow, Pipeline, Provenance, Neuroimaging
3	Ding Feng, Chaobin Huang, Kui Zhou, Peng Wang, Jin Liu, Shouyong Li	Crucial Technology Research on Pipeline Jet Cleaning Robot.	ICIRA	2008	DBLP DOI BibTeX RDF	crucial technology, robot, pipeline, cleaning
3	Shijing Wu, Qunli Li, Enyong Zhu, Jinjuan She, Ming Qin	A Hybrid Intelligent System for Pipeline Robot Navigation in Unknown Environment.	ICIRA	2008	DBLP DOI BibTeX RDF	pipeline robot, neural network, navigation, fuzzy controller
3	John Giacomoni, Tipp Moseley, Manish Vachharajani	FastForward for efficient pipeline parallelism: a cache-optimized concurrent lock-free queue.	PPOPP	2008	DBLP DOI BibTeX RDF	fastforward, multiprocessors, multicore, queue, lock-free, linearizability, nonblocking synchronization, pipeline parallel
3	John Biddiscombe, Berk Geveci, Ken Martin, Kenneth Moreland, David Thompson	Time Dependent Processing in a Parallel Pipeline Architecture.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	data-parallel visualization pipeline, time-varying data
3	Junhao Zheng, David Wu, Don Xie, Wen Gao	A Novel Pipeline Design for H.264 CABAC Decoding.	PCM	2007	DBLP DOI BibTeX RDF	VLSI, pipeline, H.264/AVC, CABAC
3	Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas	ReCycle: : pipeline adaptation to tolerate process variation.	ISCA	2007	DBLP DOI BibTeX RDF	pipeline, process variation, clock skew
3	Che-Wei Lin, Jeen-Shing Wang, Chun-Chang Yu, Ting-Yu Chen	Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network.	ICIC	2007	DBLP DOI BibTeX RDF	Synchronous pipeline design, neuro-fuzzy circuit, FPGA
3	Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda	Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS.	SBCCI	2007	DBLP DOI BibTeX RDF	analogue-to-digital converter, background (on-line) calibration, capacitor swapping technique, foreground (off-line) calibration, adaptive system, pipeline ADC
3	Jian Ruan, Zhiying Wang, Kui Dai, Yong Li 0006	Latency Estimation of the Asynchronous Pipeline Using the Max-Plus Algebra.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF	Asynchronous Pipeline, Timed Event Graph, Evolution Equation, Latency Estimation, Max-Plus Algebra
3	Anne Benoit, Yves Robert	Mapping Pipeline Skeletons onto Heterogeneous Platforms.	International Conference on Computational Science	2007	DBLP DOI BibTeX RDF	Pipeline skeleton, scheduling algorithms, throughput optimization, heterogeneous platforms, complexity results
3	Mahmoud Lotfi Anhar, Mohammad Ali Jabraeil Jamali	The Optimum Location of Delay Latches Between Dynamic Pipeline Stages.	APPT	2007	DBLP DOI BibTeX RDF	Minimum, MAL, Pipeline, Latency, Collision, Table, Reservation, Latch, Average
3	Ivan Stoianov, Lama Nachman, Samuel Madden, Timur Tokmouline	PIPENETa wireless sensor network for pipeline monitoring.	IPSN	2007	DBLP DOI BibTeX RDF	Intel mote platforms, pipeline monitoring, water supply systems, wireless sensor networks
3	Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho	Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture.	ARC	2007	DBLP DOI BibTeX RDF	adaptive pipeline, processor, Asynchronous design
3	Shiann-Tsong Sheu, Yue-Ru Chuang	A Pipeline-Based Genetic Algorithm Accelerator for Time-Critical Processes in Real-Time Systems.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	genetic algorithms (GAs), time-critical processes, optimization, Evolutionary computing, pipeline
3	Yang Xiao, Hui Chen, Mohsen Guizani	Performance Evaluation of Pipeline Paging under Paging Delay Constraint for Wireless Systems.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	Parallel, pipeline, paging, wireless systems
3	Man Wang, Zhihui Du, Yinong Chen, Zhili Cheng	A SOA Based Pipeline System to Deal with Astronomy Telescope Data.	SOSE	2006	DBLP DOI BibTeX RDF	Pipeline Data Processing, Service-Oriented Architecture, Grid Middleware
3	Eric L. Hill, Mikko H. Lipasti	Stall cycle redistribution in a transparent fetch pipeline.	ISLPED	2006	DBLP DOI BibTeX RDF	pipeline gating, microarchitecture, dynamic power, instruction fetch
3	Vahid Majidzadeh, Omid Shoaei	A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	reduced-sample-rate architectures, sigma-delta-pipeline ADCs, power optimization
3	Edward Siomacco, John L. Kundert-Gibbs, Timothy A. Davis	Developing efficient pipeline tools for animation production.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	production pipeline, computer animation, graphics
3	Nathaniel Duca, Krzysztof Niski, Jonathan Bilodeau, Matthew Bolitho, Yuan Chen, Jonathan D. Cohen	A relational debugging engine for the graphics pipeline.	ACM Trans. Graph.	2005	DBLP DOI BibTeX RDF	visualization, debugging, SQL, streaming, graphics hardware, SIMD, relational algebra, graphics pipeline
3	Arnab Roy 0001, S. K. Panda, Rajeev Kumar, P. P. Chakrabarti	A framework for systematic validation and debugging of pipeline simulators.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Simulation-based verification, dataflow equivalence, pipeline validation, design space exploration, instruction scheduling, pipelined architectures
3	Andrew Stephen McGough, Jeremy Cohen, John Darlington, Eleftheria Katsiri, William Lee, Sofia Panagiotidi, Yash Patel	An End-to-end Workflow Pipeline for Large-scale Grid Computing.	J. Grid Comput.	2005	DBLP DOI BibTeX RDF	brokering and planning, job launching, workflow pipeline, scheduling, Grid, workflow
3	Malay Kumar Pakhira, Rajat K. De	A hardware pipeline for function optimization using genetic algorithms.	GECCO	2005	DBLP DOI BibTeX RDF	hardware pipeline, pipelined GA, stochastic selection, genetic algorithms, function optimization
3	Samiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee	A 160MSPS 8-Bit Pipeline Based ADC.	VLSI Design	2005	DBLP DOI BibTeX RDF	Double sampling Sample-and-Hold, Multiplying digital-to-analog converter, Pipeline architecture, Comparator
3	Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou	A Low-Power Processor Architecture Optimized forWireless Devices.	ASAP	2005	DBLP DOI BibTeX RDF	Pipeline depth, configurable pipeline, power-adaptive processors, Low power, asynchronous circuits
3	Stavros Souravlas, Manos Roumeliotis	A Pipeline Technique for Dynamic Data Transfer on a Multiprocessor Grid.	International Journal of Parallel Programming	2004	DBLP DOI BibTeX RDF	Block-cyclic redistribution, processor classes, pipeline tasks, High Performance Fortran
3	Allan Hartstein, Thomas R. Puzak	The optimum pipeline depth considering both power and performance.	TACO	2004	DBLP DOI BibTeX RDF	Pipeline Depth, Power and Performance, Workload Specificity, Simulation
3	Shadrokh Samavi, Shahram Shirani, Nader Karimi, M. Jamal Deen	A Pipeline Architecture for Processing of DNA Microarrays Images.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	image processing, microarray, pipeline processing, DNA, morphological operations
3	Andreas Gerndt, Mark Asbach, Torsten Kuhlen, Christian H. Bischof, Stefan Lankes, Thomas Bemmerl	Conceptual design and implementation of a pipeline-based VR-system parallelized by CORBA, and comparison with existing approaches.	VRCAI	2004	DBLP DOI BibTeX RDF	visualization pipeline, virtual reality, parallelization, MPI, CORBA, CORBA
3	T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi	Fault tolerant clockless wave pipeline design.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	clockless wave pipeline, inter-wave fault, intra-wave fault, fault tolerance, reliability
3	Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda	Digital Background Gain Error Correction in Pipeline ADCs.	DATE	2004	DBLP DOI BibTeX RDF	Background Calibration, On-line Calibration, Analog-to-Digital Converter, Pipeline ADC
3	Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran	Dual-pipeline heterogeneous ASIP design.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	dual-pipeline, instruction set generation, ASIP, superscalar
3	SangMin Shim, Soo-Mook Moon	Split-Path Enhanced Pipeline Scheduling.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	multipath loops, enhanced pipeline scheduling, all-path pipelining, Instruction-level parallelism, software pipelining, modulo scheduling
3	Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai	A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	public-key crypto-system, systolic array, modular-multiplication, pipeline architecture, modular-exponentiation
3	Michael D. Powell, T. N. Vijaykumar	Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise.	ISLPED	2003	DBLP DOI BibTeX RDF	a priori current ramping, pipeline muffling, leakage, decoupling capacitors, inductive noise
3	Hajime Shimada, Hideki Ando, Toshio Shimada	Pipeline stage unification: a low-energy consumption technique for future mobile processors.	ISLPED	2003	DBLP DOI BibTeX RDF	future process technology, pipeline stage, dynamic voltage scaling, low-power consumption
3	Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda	Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages.	SBCCI	2003	DBLP DOI BibTeX RDF	Background Calibration, Analog-to-Digital Converter, Pipeline ADC, LMS algorithm
3	Jia Di, Jiann S. Yuan	Power-aware pipelined multiplier design based on 2-dimensional pipeline gating.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	2-D pipeline gating, power-awareness, array multiplier
3	Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu	Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing
3	Nian-Min Yao, Ming-Yang Zheng, Jiu-bin Ju	Pipeline: a new architecture of high performance servers.	Operating Systems Review	2002	DBLP DOI BibTeX RDF	architecture, web, pipeline, high performance, server
3	Victor Varshavsky, Vyacheslav Marakhovsky	GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor.	DELTA	2002	DBLP DOI BibTeX RDF	GALA - Globally Asynchronous Locally Arbitrary, Counterflow Pipeline Processor, Synchronous Prototype, Arbitration, Asynchronous Design
3	Kerstin Eder, Geoff Barrett	Achieving maximum performance: a method for the verification of interlocked pipeline control logic.	DAC	2002	DBLP DOI BibTeX RDF	interlock logic, pipeline stall, verification
3	Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau	Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language.	VLSI Design	2002	DBLP DOI BibTeX RDF	Pipeline Verification, Architecture Description Language
3	Eric Sprangle, Doug Carmean	Increasing Processor Performance by Implementing Deeper Pipelines. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	Pipeline depth, Pipeline
3	Ing-Jer Huang	Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	compiler instruction optimization, instruction set processor, pipeline hazards, pipeline taxonomy, synthesis
3	Iain Bate, Guillem Bernat, G. Murphy, Peter P. Puschner	Low-level analysis of a portable Java byte code WCET analysis framework.	RTCSA	2000	DBLP DOI BibTeX RDF	low-level analysis, portable Java byte code, machine-independent program flow analysis, machine-dependent timing analysis, worst-case execution frequencies, platform-dependent information, processor pipeline, platform-independent approach, Java, timing, software performance evaluation, pipeline processing, software portability, program diagnostics, worst-case execution time analysis, program constructs
3	Jakob Engblom, Andreas Ermedahl	Pipeline Timing Analysis Using a Trace-Driven Simulator.	RTCSA	1999	DBLP DOI BibTeX RDF	pipeline analysis, embedded systems, WCET, hard real-time
3	Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller	Advances of the Counterflow Pipeline Microarchitecture.	HPCA	1997	DBLP DOI BibTeX RDF	counterflow, CFPP, virtual register, architecture, pipeline, dataflow, VRP
3	David W. Matula, Asger Munk Nielsen	Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations
3	Herbert Grünbacher, Maziar Khosravipour	WinDLX and MIPSim Pipeline Simulators for Teaching Computer Architecture.	ECBS	1996	DBLP DOI BibTeX RDF	teaching computer architecture, teaching computer organisation, teaching pipelining, DLX architecture, pipeline visualisation, WinDLX, MIPSim, ECBS
3	Val Donaldson, Jeanne Ferrante	Determining Asynchronous Acyclic Pipeline Execution Times. (PDF / PS)	IPPS	1996	DBLP DOI BibTeX RDF	asynchronous pipelining, parallel execution time, loop parallelism, task graph scheduling, pipeline scheduling
3	Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga	Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline.	ASAP	1996	DBLP DOI BibTeX RDF	floating point multiply-accumulate unit, three-dimensional graphics engines, normalized space, virtual reality, virtual reality, parallelism, computer graphics, scientific visualization, matrix multiplication, matrix multiplications, data visualisation, floating point arithmetic, architectural optimizations, graphics pipeline
3	N. R. Garner, David M. Howard, P. A. Barrett, Andrew M. Tyrrell	A Parallel Processing Environment for Speech Signal Processing Applications.	PDP	1996	DBLP DOI BibTeX RDF	parallel processing environment, speech signal processing applications, 1 dimensional signal processing problem, multiple inputs, multiple outputs, interconnected signal processing functions, MIMD format, user defined structure, communication based parallel processing format, serial machine, vocoders, filterbank speech analysis, T800 transputers, parallel programming, software tool, speech recognition, pipeline processing, speech processing, transputers, transputers, Occam, speech enhancement, transputer systems, pipeline parallelism
3	Francesco Gregoretti, F. Intini, Luciano Lavagno, Roberto Passerone, Leonardo Maria Reyneri	Design and Implementation of the Control Structure of the PAPRICA-3 Processor.	PDP	1996	DBLP DOI BibTeX RDF	PAPRICA-3 processor, instruction execution, linear array processor PAPRICA-9, multi path queue structure, real-time systems, image processing, embedded systems, parallel architectures, image recognition, pipeline processing, array processor, pipeline architecture, application programs, real time image processing, control structure, image processing equipment, algorithmic efficiency
3	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Design tradeoffs in high speed multipliers and FIR filters.	VLSI Design	1996	DBLP DOI BibTeX RDF	high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
3	Jayesh Siddhiwala, Liang-Fang Chao	Scheduling conditional data-flow graphs with resource sharing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	conditional data-flow graphs, resource sharing algorithm, pipeline scheduling algorithms, loop constructs, condition vector, dynamic resource sharing, rotation scheduling technique, parallel algorithms, data structures, data structure, resource allocation, high level synthesis, high level synthesis, processor scheduling, pipeline processing, data flow graphs, loop pipelining, conditional branches
3	Sreeram Duvvuru, Siamak Arya	Evaluation of a branch target address cache.	HICSS	1995	DBLP DOI BibTeX RDF	branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes
3	Sheng-Yih Guan, Avi Bleiweiss, Richard Lipes	Parallel implementation of volume rendering on Denali graphics systems. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	computer graphic equipment, computer peripheral equipment, Denali graphics systems, 3D graphics systems, texture mapping capability, standard graphics pipeline, pipelined parallel architecture, Kubota Graphics Corporation, maximum intensity projection, iso-surface rendering, partitioning data allocation scheme, texture memory requirements, transformation and rasterization modules, frame buffer modules, parallel node, general purpose RISC processor, object parallelism, hardware ASICs, pixel memory, pixel parallelism, resource allocation, parallel architectures, volume rendering, pipeline processing, dynamic load balancing, image texture, parallel implementation, rendering (computer graphics), reduced instruction set computing, static load balancing
3	Daniel Pak-Kong Lun, Wan-Chi Siu	A Pipeline Design for the Realization of the Prime Factor Algorithm Using the Extended Diagonal Structure.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	pipeline design, prime factor algorithm, input data sequenc, data loading, parallel algorithms, parallel architectures, signal processing, digital signal processing, retrieval, Chinese Remainder Theorem, pipeline architecture, multidimensional array
3	Kok Kin Kee, Salim Hariri	Efficient communication algorithms for pipeline multicomputers.	SC	1994	DBLP BibTeX RDF	pipeline multicomputer, point-to-point routing, distributed-memory, communication algorithms
3	Ronald Jones, Imants D. Svalbe	Morphological Filtering as Template Matching.	IEEE Trans. Pattern Anal. Mach. Intell.	1994	DBLP DOI BibTeX RDF	binary morphology, pattern recognition, image processing, mathematical morphology, pipeline processing, pipeline processing, template matching, filtering and prediction theory, table lookup, lookup table, morphological filtering
3	Kow C. Chang	Stability conditions for a pipeline polling scheme in satellite communications.	Queueing Syst.	1993	DBLP DOI BibTeX RDF	cyclic-service system, pipeline polling, Stability, satellite communications, reservation scheme
3	Ben-Kwei Jang, Roland T. Chin	One-Pass Parallel Thinning: Analysis, Properties, and Quantitative Evaluation.	IEEE Trans. Pattern Anal. Mach. Intell.	1992	DBLP DOI BibTeX RDF	one-pass parallel thinning, unit-width convergence, pipeline processing model, skeletal connectivity, parallel algorithms, image recognition, shape analysis, pipeline processing, convergence of numerical methods, noise immunity, medial axis approximation
3	Veljko M. Milutinovic, David A. Fura, Walter A. Helbig	Pipeline Design Tradeoffs in a 32-bit Gallium Arsenide Microprocessor.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	instruction pipeline design, single-chip GaAs microprocessor, application-related parameters, pipelined memory pipeline, III-V semiconductors, performance evaluation, microprocessor chips, instruction sets, 32 bit, GaAs, gallium arsenide
3	Zbigniew M. Wójcik, Barbara E. Wójcik	Rough Grammar For Efficient and Fault-Tolerant Computing on a Distributed System.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	global load balancing, dynamic task scheduling, multiprocessor machine, rough grammar, rough grammar production rules, pipeline fashion, statically scheduled multiprocessor, decentralized methodology, scheduling, fault tolerance, parallel processing, distributed computation, fault-tolerant computing, fault tolerant computing, concurrent program, grammars, pipeline processing
3	Kai Hwang, Zhiwei Xu	Multipipeline Networking for Compound Vector Processing.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	compound vector processing, multipipeline networking, pipeline chaining, pipeline nets, run-time techniques, Livermore loops, performance evaluation, performance analysis, parallel programming, compilation, parallel architectures, programming, program compilers, pipeline processing, scientific programs, vector-processing, systolization
3	Richard G. Cooper	The Distributed Pipeline.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Array of computers, distributed pipeline (DP), multiple-instruction multiple-data-stream (MIMD) computer, distributed computer, multiprocessor, pipeline, computer network, computer architecture, microprocessor, microcomputer
2	Shenglin Gui, Lei Luo	End-to-End Schedulability Analysis for Bi-directional Real-Time Multistage Pipeline.	ISPA	2011	DBLP DOI BibTeX RDF	generalized pipeline system, end-to-end schedulability analysis
2	Xiaoqiang Li, Hong An, Gu Liu, Wenting Han, Mu Xu, Wei Zhou, Qi Li	A Non-blocking Programming Framework for Pipeline Application on Multi-core Platform.	ISPA	2011	DBLP DOI BibTeX RDF	pipeline, programming model, work-stealing
2	Cyril Soler, Olivier Hoel, Frank Rochet	A deferred shading pipeline for real-time indirect illumination.	SIGGRAPH Talks	2010	DBLP DOI BibTeX RDF
2	Akash Garg, Kyle Maxwell	Seamless fracture in a production pipeline.	SIGGRAPH Talks	2010	DBLP DOI BibTeX RDF
2	Ian J. Coony, Brian Silva, Bruce Wright, Andrew Kinney	Prep and landing set'm and forget'm: a motion graphics pipeline for effects.	SIGGRAPH Talks	2010	DBLP DOI BibTeX RDF
2	Bo Wang, Shifeng Shang, Qiming Fang, Weimin Zheng	Parallel Task Developing Based on Software Pipeline in Multicore System.	ISPA	2010	DBLP DOI BibTeX RDF	parallel task building, software pipeline, multicore system
2	Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam	Automatic multithreaded pipeline synthesis from transactional datapath specifications.	DAC	2010	DBLP DOI BibTeX RDF	automatic pipelining, datapath specification, design exploration of x86 processor pipelines, multithreading, hardware synthesis