Search results for "pipelined analog to digital converter"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee	A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Jin-Fu Lin, Soon-Jyh Chang	A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique.	ISCAS	2006	DBLP DOI BibTeX RDF
2	K. Folkesson, C. Svensson, B. Knuthammar, A. Dreyfert	A high-level dynamic-error model of a pipelined analog-to-digital converter.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen	A new CCII-based pipelined analog to digital converter.	ISCAS	2005	DBLP DOI BibTeX RDF
2	SeongHwan Cho, Sungmin Ock, Sang-Hoon Lee, Joonsuk Lee	A low power pipelined analog-to-digital converter using series sampling capacitors.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi	A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique.	ISLPED	2003	DBLP DOI BibTeX RDF	CMOS analog circuit, Slew Boost technique, class AB, low power, high speed, operational amplifier, pipelined analog to digital converter, ultra low voltage
2	Babak Nejati, Omid Shoaei	A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-um CMOS.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Kuan-Yu Lin, Ji-Eun Jang, Ching-Hsuan Hsieh, Yung-Pin Lee	A pipelined analog-to-digital converter using incomplete-settling-without-slewing technique.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Wenxiao Feng, Tiejun Lu, Zongmin Wang	Analysis and Design of Fully Differential Gain-Boosted Op-amp for 14bit 100MS/s Pipelined Analog-to-Digital Converter.	NCM	2009	DBLP DOI BibTeX RDF	fully differential op-amp, folded cascode, boosting amplifier, pipelined ADC
1	Santanu Sarkar 0002, A. Ghosh, Swapna Banerjee	A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Guo-Ming Sung, Jyi-Hrong Tzeng, Chen-Shen Liao, Shih-Chieh Shu	A Low-power 7-b 33-Msamples/s Switched-current Pipelined ADC for Motor Control.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Cristiano Azzolini, P. Milanesi, Andrea Boni	Accurate transient response model for automatic synthesis of high-speed operational amplifiers.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Mohammad Taherzadeh-Sani, Anas A. Hamoui	Analysis of dynamic element matching (DEM) in pipelined ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Fernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli	Mixed signal design space exploration through analog platforms.	DAC	2005	DBLP DOI BibTeX RDF
1	Reza Lotfi, Mohammad Taherzadeh-Sani, Omid Shoaei	Power consumption issues in high-speed high-resolution pipelined A/D converters.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Hsin-Hung Ou, Bin-Da Liu	A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Shigeto Tanaka, Yuji Gohda, Yasuhiro Sugimoto	The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Babak Nejati, Omid Shoaei	Systematic design of the pipelined analog-to-digital converter with radix<2.	Microelectronics Journal	2004	DBLP DOI BibTeX RDF
1	Babak Nejati, Omid Shoaei	A 10-bit, 3.3-V, 60MSample/s, combined radix<2 and 1.5-bit/stage pipelined analog-to-digital converter.	ISCAS	2004	DBLP BibTeX RDF
1	Arun Ravindran, Anup Savla, Jennifer Leonard	Digital error correction and calibration of gain non-linearities in a pipelined ADC.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Seyed Mojtaba Atarodi	A 1.8-v high-speed 13-bit pipelined analog to digital converter for digital IF applications.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Jipeng Li, Un-Ku Moon	High-speed pipelined A/D converter using time-shifted CDS technique.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Yu-Yee Liow, Chung-Yu Wu	The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Z. Tao, M. Keramat	A 10-bit 100-MS/s 50 mW CMOS A/D converter.	ISCAS	2002	DBLP DOI BibTeX RDF
1	B. E. Jonsson, Hannu Tenhunen	A 3 V switched-current pipelined analog-to-digital converter in a 5 V CMOS process.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Mehdi Ehsanian, Bozena Kaminska, Karim Arabi	A new digital test approach for analog-to-digital converter testing.	VTS	1996	DBLP DOI BibTeX RDF	digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
1	John Wu, Bosco Leung, Sehat Sutarja	A Mismatch Independent DNL Pipelined Analog to Digital Converter.	ISCAS	1994	DBLP BibTeX RDF