Search results for "pipelining"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.	ASP-DAC	2007	DBLP DOI BibTeX RDF	graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining
4	Smita Bakshi, Daniel Gajski	Performance-constrained hierarchical pipelining for behaviors, loops, and operations.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	DSP (digital signal processing) systems, hierarchical pipelining, pipelined systems, scheduling, component selection, loop pipelining
4	Dragan Milicev, Zoran Jovanovic	A Formal Model of Software Pipelining Loops with Conditions. (PDF / PS)	IPPS	1997	DBLP DOI BibTeX RDF	software pipelining loops, PSP model, parallel programming, finite state machine, formal model, software pipelining, parallelizing loops, conditional branches
4	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Design tradeoffs in high speed multipliers and FIR filters.	VLSI Design	1996	DBLP DOI BibTeX RDF	high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
3	Haitao Wei, Junqing Yu, Huafei Yu, Guang R. Gao	Minimizing communication in rate-optimal software pipelining for stream programs.	CGO	2010	DBLP DOI BibTeX RDF	dfbrook, multi-core, software pipelining, cell processor, stream programs
3	Jean-Baptiste Tristan, Xavier Leroy	A simple, verified validator for software pipelining.	POPL	2010	DBLP DOI BibTeX RDF	software pipelining, translation validation, verified compilers, symbolic evaluation
3	Hui Liu, Zili Shao, Meng Wang, Junzhao Du, Chun Jason Xue, Zhiping Jia	Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Periodic dependent tasks, Scheduling, Multimedia, Real-time, Dynamic voltage scaling (DVS), Multi-core, Software pipelining, Retiming
3	G. Seetharaman, B. Venkataramani	Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.	TRETS	2009	DBLP DOI BibTeX RDF	FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA
3	Ram Rangan, Neil Vachharajani, Guilherme Ottoni, David I. August	Performance scalability of decoupled software pipelining.	TACO	2008	DBLP DOI BibTeX RDF	Decoupled software pipelining, performance analysis
3	Sebastian Winkel, Rakesh Krishnaiyer, Robyn Sampson	Latency-tolerant software pipelining in a production compiler.	CGO	2008	DBLP DOI BibTeX RDF	latency-tolerant scheduling, load clustering, compiler, code generation, prefetching, software pipelining, modulo scheduling, memory latency, memory-level parallelism, itanium, epic
3	Hyeong Seog Kim, In Soon Cho, Heon Young Yeom	A Task Pipelining Framework for e-Science Workflow Management Systems.	CCGRID	2008	DBLP DOI BibTeX RDF	task pipelining, workflow manager
3	Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao	Single-dimension software pipelining for multidimensional loops.	TACO	2007	DBLP DOI BibTeX RDF	Software pipelining, loop transformation, modulo scheduling
3	Sid Ahmed Ali Touati	On the Periodic Register Need in Software Pipelining.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Periodic Register Requirement, MAXLIVE, Periodic Register Sufficiency, Stage Scheduling, Instruction Level Parallelism, Software Pipelining
3	Sevin Fide, Stephen Jenks	A middleware approach for pipelining communications in clusters.	Cluster Computing	2007	DBLP DOI BibTeX RDF	Cluster communications, Middleware, MPI, Pipelining
3	Takuya Miyamaru, Hiroshi Mineno, Yoshiaki Terashima, Yuichi Tokunaga, Tadanori Mizuno	State-Based Pipelining for Reprogramming Wireless Sensor Networks.	KES	2007	DBLP DOI BibTeX RDF	Wireless sensor network, Pipelining, Reprogramming
3	Xue Yang, Nitin H. Vaidya	A Wireless MAC Protocol Using Implicit Pipelining.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	access energy cost, packet access delay, wireless LANs, pipelining, IEEE 802.11, multihop networks, channel utilization, Multiple access control (MAC)
3	Yuan-man Tong, Zhiying Wang, Kui Dai, Hongyi Lu	Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining.	Inscrypt	2006	DBLP DOI BibTeX RDF	WDDL, power analysis resistant, block cipher, design flow, Wave-pipelining
3	Anuja Jayraj Thakkar, Abdel Ejnioui	Pipelining of double precision floating point division and square root operations.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	FPGA, pipelining, floating point, division, square root
3	Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria	Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	multiphase, sequential circuit, software pipelining, clock, Retiming
3	Shih-Hao Wang, Wen-Hsiao Peng, Yuwen He, Guan-Yi Lin, Cheng-Yi Lin, Shih-Chien Chang, Chung-Neng Wang, Tihao Chiang	A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	advanced video coding (AVC), joint video team (JVT), software-hardware co-implementation, MB level pipelining, H.264, MPEG-4, task partition
3	Daniel Kästner, Markus Pister	Generic Software Pipelining at the Assembly Level.	SCOPES	2005	DBLP DOI BibTeX RDF	PROPAN, software pipelining, modulo scheduling, postpass optimization
3	Mario R. Casu, Luca Macchiarulo	Floorplan assisted data rate enhancement through wire pipelining: a real assessment.	ISPD	2005	DBLP DOI BibTeX RDF	through-put, systems-on-chip, floorplanning, wire pipelining
3	João M. P. Cardoso	Dynamic loop pipelining in data-driven architectures.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	compilation, reconfigurable computing, software pipelining, dataflow, data-driven architectures
3	Won So, Alexander G. Dean	Complementing software pipelining with software thread integration.	LCTES	2005	DBLP DOI BibTeX RDF	TI C6000, DSP, software pipelining, VLIW, stream programming, coarse-grain parallelism, software thread integration
3	Noureddine Chabini, Wayne Wolf	An approach for integrating basic retiming and software pipelining.	EMSOFT	2004	DBLP DOI BibTeX RDF	embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size
3	Jason Cong, Yiping Fan, Zhiru Zhang	Architecture-level synthesis for automatic interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding
3	Han-Saem Yun, Jihong Kim, Soo-Mook Moon	Time Optimal Software Pipelining of Loops with Control Flows.	International Journal of Parallel Programming	2003	DBLP DOI BibTeX RDF	compiler optimization, instruction-level parallelism, software pipelining, VLIW
3	Akshay Sharma, Carl Ebeling, Scott Hauck	PipeRoute: a pipelining-aware router for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	BFS, PipeRoute, retimed circuits, routing, pipelining, minimum spanning tree, retiming, pipelined circuits
3	SangMin Shim, Soo-Mook Moon	Split-Path Enhanced Pipeline Scheduling.	IEEE Trans. Parallel Distrib. Syst.	2003	DBLP DOI BibTeX RDF	multipath loops, enhanced pipeline scheduling, all-path pipelining, Instruction-level parallelism, software pipelining, modulo scheduling
3	Jiang Xu, Wayne Wolf	Wave pipelining for application-specific networks-on-chips.	CASES	2002	DBLP DOI BibTeX RDF	system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance
3	William Chow, Jonathan Rose	EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits.	FPGA	2002	DBLP DOI BibTeX RDF	event horizon, manual placement and pipelining, FPGA, programmable logic
3	Han-Saem Yun, Jihong Kim, Soo-Mook Moon	Optimal software pipelining of loops with control flows.	ICS	2002	DBLP DOI BibTeX RDF	instruction-level parallelism, software pipelining, VLIW
3	Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck	Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors.	VLSI Design	2002	DBLP DOI BibTeX RDF	coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation
3	Ramaswamy Govindarajan, Guang R. Gao, Palash Desai	Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks.	VLSI Signal Processing	2002	DBLP DOI BibTeX RDF	buffer minimization, Digital Signal Processing (DSP) computation, Multi-Rate Software Pipelining, Regular Stream Flow Graphs, software pipelining, dataflow graphs
3	Iffat H. Kazi, David J. Lilja	Coarse-Grained Thread Pipelining: A Speculative Parallel Execution Model for Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distrib. Syst.	2001	DBLP DOI BibTeX RDF	Runtime parallelization, thread pipelining, superthreaded architecture, shared-memory multiprocessors, speculative execution, coarse-grained parallelization
3	François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer	Optimal design of synchronous circuits using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	software pipelining, retiming, Resynthesis
3	Elana D. Granston, Eric Stotzer, Joe Zbiciak	Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture.	LCTES/OM	2001	DBLP DOI BibTeX RDF	WHILE loops, software pipelining, digital signal processors, VLIW architectures
3	Cagdas Akturan, Margarida F. Jacome	RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors.	CODES	2001	DBLP DOI BibTeX RDF	embedded systems, software pipelining, retiming, optimizing compilers, VLIW processors
3	Pierre-Yves Calland, Alain Darte, Yves Robert	Circuit Retiming Applied to Decomposed Software Pipelining.	IEEE Trans. Parallel Distrib. Syst.	1998	DBLP DOI BibTeX RDF	circuit retiming, Software pipelining, list scheduling, modulo scheduling, cyclic scheduling
3	James K. Huggins, David Van Campenhout	Specification and verification of pipelining in the ARM2 RISC microprocessor.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	ARM processor, formal verification, pipelining, abstract state machines, design verification, pipelined processors
3	Soo-Mook Moon, Kemal Ebcioglu	Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar
3	Tao Yu, Zhizhong Tang, Chihong Zhang, Jun Luo	Control Mechanism for Software Pipelining on Nested Loop.	APDC	1997	DBLP DOI BibTeX RDF	ILSP, software pipelining, VLIW, dataflow, nested loop
3	Ireneusz Karkowski, Henk Corporaal	Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining.	IEEE PACT	1997	DBLP DOI BibTeX RDF	heterogenous multiprocessor embedded system design, functional pipelining, embedded program mapping, ANSI C program, application specific processor pipeline, frequency tracking system, two-processor system, highly optimized single core solution, architecture, multiprocessing systems, instruction level parallelism, speedup, efficient algorithm, loops
3	Smita Bakshi, Daniel Gajski	A Scheduling and Pipelining Algorithm for Hardware/Software Systems. (PDF / PS)	ISSS	1997	DBLP DOI BibTeX RDF	throughput-constrained, scheduling, pipelining, high-performance, Hardware/software codesign
3	G. Enrique Fernandez, R. Sridhar	Dual rail static CMOS architecture for wave pipelining.	VLSI Design	1996	DBLP DOI BibTeX RDF	dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
3	Peter Pfahler, Georg Piepenbrock	A Comparison of Modulo Scheduling Techniques for Software Pipelining.	CC	1996	DBLP DOI BibTeX RDF	Instruction Level Parallelism, Software Pipelining, VLIW, Superscalar Processors
3	Jian Wang, Guang R. Gao	Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops.	CC	1996	DBLP DOI BibTeX RDF	Very Long Instruction Word(VLIW), Instruction-Level Parallelism, Software Pipelining, Superscalar, Nested Loop, Loop Scheduling, Fine-Grain Parallelism
3	Alexander Aiken, Alexandru Nicolau, Steven Novack	Resource-Constrained Software Pipelining.	IEEE Trans. Parallel Distrib. Syst.	1995	DBLP DOI BibTeX RDF	Software pipelining, instruction scheduling, program optimization, global scheduling, fine-grain parallelism
3	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
3	Fermín Sánchez	Time-Constrained Loop Pipelining.	ICCAD	1995	DBLP DOI BibTeX RDF	timing and resource contraints, register optimization, scheduling, loop pipelining
3	Siamak Arya, Howard Sachs, Sreeram Duvvuru	An architecture for high instruction level parallelism.	HICSS	1995	DBLP DOI BibTeX RDF	high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, branches, program control structures, registers, functional units, multiple instructions, conditional execution
3	KyungHi Chang, XuDuan Lin	Ultra-high-speed digital filtering algorithm for video signal processing. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	ultra-high-speed digital filtering algorithm, improved minimum-order augmented pipelining, IMAP algorithm, clustered look-ahead technique, augmented pipelining order, undesirable quantization effects, 1-D IMAP digital filter, 2-D structure, bandwidth reduction algorithm, motion estimation, motion estimation, pipeline processing, minimization, minimisation, video signal processing, video signal processing, interference suppression, two-dimensional digital filters, spatio-temporal filtering
3	Jian Wang, Andreas Krall, M. Anton Ertl, Christine Eisenbeis	Software pipelining with register allocation and spilling.	MICRO	1994	DBLP DOI BibTeX RDF	instruction-level parallelism, register allocation, software pipelining, loop scheduling, register spilling
3	B. Ramakrishna Rau	Iterative modulo scheduling: an algorithm for software pipelining loops.	MICRO	1994	DBLP DOI BibTeX RDF	software pipelining, instruction scheduling, modulo scheduling, loop scheduling
3	Bogong Su, Stanley Habib, Wei Zhao, Jian Wang, Youfeng Wu	A study of pointer aliasing for software pipelining using run-time disambiguation.	MICRO	1994	DBLP DOI BibTeX RDF	compensation code, pointer aliasing, rerollability, run-time disambiguation, software pipelining
3	Reese B. Jones, Vicki H. Allan	Software pipelining: a comparison and improvement.	MICRO	1990	DBLP DOI BibTeX RDF	recognition of parallelism, software pipelining, operation scheduling
3	Barron C. Housel	Pipelining: A Technique for Implementing Data Restructurers.	ACM Trans. Database Syst.	1979	DBLP DOI BibTeX RDF	database conversion, pipelining, deadlock, process scheduling, data translation
2	Jialu Huang, Arun Raman, Thomas B. Jablin, Yun Zhang, Tzu-Han Hung, David I. August	Decoupled software pipelining creates parallelization opportunities.	CGO	2010	DBLP DOI BibTeX RDF	DSWP, enabling transformation, parallelization, multicore, speculation
2	Matthias Függer, Andreas Dielacher, Ulrich Schmid	How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining.	EDCC	2010	DBLP DOI BibTeX RDF	modeling approaches, VLSI, pipelining, clock synchronization, Fault-tolerant distributed algorithms
2	Tang-Hsun Tu, Chih-wen Hsueh	Batch-Pipelining for H.264 Decoding on Multicore Systems.	DCC	2010	DBLP DOI BibTeX RDF	Optimization, Multimedia, Pipelining, Multicore, H.264
2	Maxwell Walton, Gary Gréwal, Gerarda Darlington	Parallel FPGA-based implementation of scatter search.	GECCO	2010	DBLP DOI BibTeX RDF	0-1 knapsack problem, field programmable gate arrays, pipelining, hardware acceleration, data parallelism, scatter search
2	Eddy Z. Zhang, Yunlian Jiang, Ziyu Guo, Xipeng Shen	Streamlining GPU applications on the fly: thread divergence elimination through runtime thread-data remapping.	ICS	2010	DBLP DOI BibTeX RDF	CPU-GPU pipelining, thread divergence, thread-data remapping, GPGPU, data transformation
2	Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon	Pipelining Saturated Accumulation.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
2	Yong Dou, Guiming Wu, Jinhui Xu, Xingming Zhou	A coarse-grained reconfigurable computing architecture with loop self-pipelining.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	reconfigurable computing, data driven, loop pipelining, register promotion
2	Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee	A software pipelining algorithm in high-level synthesis for FPGA architectures.	ISQED	2009	DBLP DOI BibTeX RDF
2	Yanqin Yang, Meng Wang, Zili Shao, Minyi Guo	Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems.	CSE	2009	DBLP DOI BibTeX RDF
2	Zubair Nawaz, Thomas Marconi, Koen Bertels, Todor Stefanov	Flexible pipelining design for recursive variable expansion.	IPDPS	2009	DBLP DOI BibTeX RDF
2	Yoshiyuki Yamashita, Masato Tsuru	Implementing Fast Packet Filters by Software Pipelining on x86 Processors.	APPT	2009	DBLP DOI BibTeX RDF
2	Andreas Dielacher, Matthias Függer, Ulrich Schmid	Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining.	PODC	2009	DBLP DOI BibTeX RDF	modeling approaches, VLSI, pipelining, clock synchronization, fault-tolerant distributed algorithms
2	Mohammed Fellahi, Albert Cohen	Software Pipelining in Nested Loops with Prolog-Epilog Merging.	HiPEAC	2009	DBLP DOI BibTeX RDF
2	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
2	Junchang Wang, Haipeng Cheng, Bei Hua, Xinan Tang	Practice of parallelizing network applications on multi-core architectures.	ICS	2009	DBLP DOI BibTeX RDF	application-level protocol processing, deep content inspection, lock-free data structures, multi-core parallelization, pipelining implementation, tcp/ip protocol processing
2	Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil	Synergistic execution of stream programs on multicores with accelerators.	LCTES	2009	DBLP DOI BibTeX RDF	CUDAa, partitioning, software pipelining, stream programming, GPU programming
2	Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh	Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung	Outer Loop Pipelining for Application Specific Datapaths in FPGAs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng	A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Chua-Chin Wang, Gang-Neng Sung, Pai-Li Liu	Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	data transition detection, CLA, pipeline, power-aware, ANT
2	Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J. Bridges, David I. August	Parallel-stage decoupled software pipelining.	CGO	2008	DBLP DOI BibTeX RDF	doall, dswp, tlp, automatic parallelization, multi-core architectures, pipelined parallelism
2	Yoonjin Kim, Rabi N. Mahapatra	Reusable context pipelining for low power coarse-grained reconfigurable architecture.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Yuanming Zhang, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba	Clustered Decoupled Software Pipelining on Commodity CMP.	ICPADS	2008	DBLP DOI BibTeX RDF
2	Jie Shao, Ning Ye, Xiao-Yan Zhang	An IEEE Compliant Floating-Point Adder with the Deeply Pipelining Paradigm on FPGAs.	CSSE	2008	DBLP DOI BibTeX RDF
2	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	High-throughput interconnect wave-pipelining for global communication in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF
2	Mark Muir, Tughrul Arslan, Iain Lindsay	Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications.	DATE	2008	DBLP DOI BibTeX RDF
2	Zhikun Wang, Dan Feng, Ke Zhou, Fang Wang	PCOW: Pipelining-Based COW Snapshot Method to Decrease First Write Penalty.	GPC	2008	DBLP DOI BibTeX RDF
2	Timothy Kam, Michael Kishinevsky, Jordi Cortadella, Marc Galceran Oms	Correct-by-construction microarchitectural pipelining.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Ching-Wen Chen, Chuan-Chi Weng, Po-Jung Chen	Design of a Low-Power and Low-Latency MAC Protocol with Nodes Grouping and Transmission Pipelining in Wireless Sensor Networks.	VTC Spring	2008	DBLP DOI BibTeX RDF
2	Suhyun Kim, Soo-Mook Moon	Rotating register allocation with multiple rotating branches.	ICS	2008	DBLP DOI BibTeX RDF	rotating register, register allocation, software pipelining
2	Mounira Bachir, Sid Ahmed Ali Touati, Albert Cohen	Post-pass periodic register allocation to minimise loop unrolling degree.	LCTES	2008	DBLP DOI BibTeX RDF	embedded code optimisation, periodic register allocation, software pipelining, loop unrolling
2	Hongbo Rong, Alban Douillet, Guang R. Gao	Register allocation for software pipelined multidimensional loops.	ACM Trans. Program. Lang. Syst.	2008	DBLP DOI BibTeX RDF	register allocation, Software pipelining
2	Abhishek Das, William J. Dally	Stream Scheduling: A Framework to Manage Bulk Operations in Memory Hierarchies.	Euro-Par	2008	DBLP DOI BibTeX RDF	Stream Scheduling, Bulk Operations, Sequoia, GSOP Memory Hierarchy, Tunables, Software Pipelining
2	Roger F. Woods, John V. McCanny, John G. McWhirter	From Bit Level Systolic Arrays to HDTV Processor Chips.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	SoC architectures, DSP systems, pipelining, systolic arrays
2	Ricardo Menotti, Eduardo Marques, João M. P. Cardoso	Aggressive Loop Pipelining for Reconfigurable Architectures.	FPL	2007	DBLP DOI BibTeX RDF
2	Nan Wang, Azeez Sanusi, Peiyi Zhao, Shaheen Mohamed, Magdy A. Bayoumi	PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design.	SiPS	2007	DBLP DOI BibTeX RDF
2	Neil Vachharajani, Ram Rangan, Easwaran Raman, Matthew J. Bridges, Guilherme Ottoni, David I. August	Speculative Decoupled Software Pipelining.	PACT	2007	DBLP DOI BibTeX RDF
2	Colin J. Ihrig, Justin Stander, Alex K. Jones	Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions.	IPDPS	2007	DBLP DOI BibTeX RDF
2	Yoshiyuki Yamashita, Masato Tsuru	Software Pipelining for Packet Filters.	HPCC	2007	DBLP DOI BibTeX RDF
2	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining.	DATE	2007	DBLP DOI BibTeX RDF
2	A. Neslin Ismailoglu, Murat Askar	Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Power Consumption Analysis of Flip-flop Based Interconnect Pipelining.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Yong Dou, Jinhui Xu, Guiming Wu	The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.	ARC	2007	DBLP DOI BibTeX RDF