Search results for "power"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Suresh Rajgopal	Challenges in Low Power Microprocessor Design.	VLSI Design	1996	DBLP DOI BibTeX RDF	power benchmarks, latch power, idle power, active power, clock enabling, max power, thermal power, transient power, low-power, clock gating, microprocessor design, di/dt
9	Massoud Pedram	Power minimization in IC design: principles and applications.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	adiabatic circuits, dynamic power dissipation, low power layout, low power synthesis, lower-power design, power analysis and estimation, power minimization and management, silicon-on-insulator technology, switched capacitance, synthesis, system design, power management, layout, probabilistic analysis, symbolic simulation, CMOS circuits, switching activity, statistical sampling, computer-aided design of VLSI, gated clocks, energy-delay product
8	William Lloyd Bircher, Lizy K. John	Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events.	ISPASS	2007	DBLP DOI BibTeX RDF	power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model
8	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee	Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
8	Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Fast power estimation for deterministic input streams.	ICCAD	1997	DBLP DOI BibTeX RDF	accurate power waveforms, average power, deterministic input streams, fast power estimation, multi level simulation engine, realistic input stimuli, time domain power waveform, typical usage patterns, sequential circuits, combinational circuits, power consumption, power dissipation, digital systems, computational efficiency
7	Charles Lefurgy, Xiaorui Wang, Malcolm Allen-Ware	Power capping: a prelude to power shifting.	Cluster Computing	2008	DBLP DOI BibTeX RDF	Power capping, Power shifting, Power budget, Power supplies, Power management, Feedback control, Servers, Provisioning
7	Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung	Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	IPI power model, black-box power model, prefetch power model, processor power modeling, software power estimation
7	Ju Wang, Jonathan C. L. Liu	An iterative power allocation algorithm in OFDM system based on power relaxation.	ICME	2005	DBLP DOI BibTeX RDF	discrete space power-rate vector, iterative power allocation algorithm, multiuser OFDM system, power relaxation, bit loading, ideal channel coding, negative power transmission, orthogonal frequency division multiplexing, objective function, power constraint
7	Jian Liu, Rafic Z. Makki	Power supply current detectability of SRAM defects.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect
7	Joep L. W. Kessels	VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, VLSI programming, low-power asynchronous Reed-Solomon decoder, DCC player, Tangram, minimal power dissipation, low-power cost-effective design, VLSI, logic programming, power consumption, power consumption, asynchronous circuits, asynchronous circuit, decoding, Reed-Solomon codes
7	Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye	A technique to determine power-efficient, high-performance superscalar processors.	HICSS	1995	DBLP DOI BibTeX RDF	high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation
7	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
6	Nandish Ashutosh Mehta, Gururaj V. Naik, Bharadwaj S. Amrutur	In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits.	ISLPED	2010	DBLP DOI BibTeX RDF	DVTS loop, in-situ power monitor, power optimum point, variable body bias, variable supply voltage, low power, ground bounce
6	Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken	The challenges of implementing fine-grained power gating.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating
6	Anita Lungu, Pradip Bose, Alper Buyuktosunoglu, Daniel J. Sorin	Dynamic power gating with quality guarantees.	ISLPED	2009	DBLP DOI BibTeX RDF	execution units, low power, power management, microarchitecture, power gating
6	Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura	Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption.	PATMOS	2008	DBLP DOI BibTeX RDF	Arrival time variation, coupling power, power estiamtion, low power coding, on-chip bus
6	Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos	A multi-model power estimation engine for accuracy optimization.	ISLPED	2007	DBLP DOI BibTeX RDF	power macromodeling, powerSC, low power design, systemC, power estimation
6	Quming Zhou, Lin Zhong, Kartik Mohanram	Power signal processing: a new perspective for power analysis and optimization.	ISLPED	2007	DBLP DOI BibTeX RDF	power simulation, power, signal processing, power analysis
6	Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou	Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost.	ASP-DAC	2007	DBLP DOI BibTeX RDF	hardware modifications, software modifications, hardware timers, interrupt controllers, software/device driver, distributed software-defined radio system, hardware measurements, power manager, power management, multiprocessor systems, distributed real-time systems, power constraints, low-power embedded systems
6	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti	Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.	VTS	2007	DBLP DOI BibTeX RDF	Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling
6	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	ILP models for simultaneous energy and transient power minimization during behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power
6	Axel Reimer, Arne Schulz, Wolfgang Nebel	Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs.	ISLPED	2006	DBLP DOI BibTeX RDF	FPGA power estimation, RT-level power modeling, high-level power estimation
6	Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Considering process variations during system-level power analysis.	ISLPED	2006	DBLP DOI BibTeX RDF	system-on-chip, low power design, process variations, power analysis, power estimation
6	John Wei, Chris Rowen	Implementing low-power configurable processors: practical options and tradeoffs.	DAC	2005	DBLP DOI BibTeX RDF	PVT (process, voltage, temperature), configurable embedded processor, dynamic power efficiency, scaled VDD, low-power, leakage power, SOC (system on chip), dynamic power
6	Tim Fox, Lou Covey, Susan Mack, David Heacock, Ed P. Huijbregts, Vess Johnson, Avner Kornfeld, Andrew Yang, Paul S. Zuchowski	Should our power approach be current?	DAC	2005	DBLP DOI BibTeX RDF	low-power design, energy consumption, power analysis, leakage current, dynamic power, static power
6	Stefano Gregori, Yunlei Li, Huijuan Li, Jin Liu, Franco Maloberti	2.45 GHz power and data transmission for a low-power autonomous sensors platform.	ISLPED	2004	DBLP DOI BibTeX RDF	RF to DC power conversion, low power clock and data recovery, microwave power transmission, wireless sensor
6	Michael Eiermann, Walter Stechele	Novel modeling techniques for RTL power estimation.	ISLPED	2002	DBLP DOI BibTeX RDF	RTL macromodels, low power, power estimation, power modeling
6	Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh	Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources.	PACS	2002	DBLP DOI BibTeX RDF	power-aware scheduling/task motion, timing/power constraint modeling, power/performance range, system-level design
6	Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu	Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	distribution-graph based approach, extended tree growing technique, power-constrained block-test scheduling, unequal-length block-test scheduling, power dissipation constraints, test concurrency, assigned power dissipation limits, balanced test power dissipation, least mean square error function, global priority function, system-level test scheduling algorithm, scheduling, VLSI, fault diagnosis, logic testing, high level synthesis, integrated circuit testing, automatic test pattern generation, trees (mathematics), least mean squares methods
6	Hangu Yeo, Yu Hen Hu	A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation.	ASAP	1996	DBLP DOI BibTeX RDF	matching criterion, real-time block based motion estimation, video signals, binary level matching criterion, bit-wise comparison, processor level design, total power consumption, motion estimation, power consumption, power consumption, video signal processing, combinational logic, low power architecture
6	Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee	Instruction Level Power Analysis and Optimization of Software.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power software, embedded systems, low power design, embedded software, power estimation, power optimization
6	Inki Hong, Miodrag Potkonjak	Power optimization in disk-based real-time application specific systems.	ICCAD	1996	DBLP DOI BibTeX RDF	design process abstractions, disk data assignment, electronic components, magnetic disks, mechanical-electronic subsystems, power consumption model, real-time application specific systems, task scheduling, power optimization, power reduction, power minimization, magnetic disc storage, disk drives
6	Enric Musoll, Jordi Cortadella	Scheduling and resource binding for low power.	ISSS	1995	DBLP DOI BibTeX RDF	data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding
6	Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore	The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz
5	Ajith Amerasekera	Ultra low power electronics in the next decade.	ISLPED	2010	DBLP DOI BibTeX RDF	low-power electronics, power management
5	Mondira (Mandy) Deb Pant	Microprocessor power delivery challenges in the Nano-Era.	ISLPED	2010	DBLP DOI BibTeX RDF	power delivery, power, microprocessors
5	David Meisner, Thomas F. Wenisch	Peak power modeling for data center servers with switched-mode power supplies.	ISLPED	2010	DBLP DOI BibTeX RDF	switched-mode power supplies, peak power
5	S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay	Customizing pattern set for test power reduction via improved X-identification and reordering.	ISLPED	2010	DBLP DOI BibTeX RDF	don't care bits, runtime leakage power, vector reordering, x-fill, dynamic power
5	Faraz Ahmad, T. N. Vijaykumar	Joint optimization of idle and cooling power in data centers while maintaining response time.	ASPLOS	2010	DBLP DOI BibTeX RDF	cooling power, idle power, power management, response time, data center
5	Antonello Monti, Ferdinanda Ponci	Power Grids of the Future: Why Smart Means Complex.	COMPENG	2010	DBLP DOI BibTeX RDF	Power Control, Power Systems, Power Electronics, Power distribution
5	Mackenzie R. Scott, Rajeevan Amirtharajah	Pulse width modulation for reduced peak power full-swing on-chip interconnect.	ISLPED	2009	DBLP DOI BibTeX RDF	low power interconnect, peak power, pulse width modulation
5	Soheil Modirzadeh, Brian Fuller, Sandeep Mirchandani, Jon McDonald, Ran Avinun, Camille Kokozaki	It is all about power analysis, exploration and trade-offs.	ISLPED	2009	DBLP DOI BibTeX RDF	IDT, NXP, broadcom, cadence, system design and verification, technical panel, low power, low power design
5	Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu	Power-management-based Chien search for low power BCH decoder.	ISLPED	2009	DBLP DOI BibTeX RDF	BCH decoder, Chien search, low power, power management
5	Milan Milenkovic, Enrique Castro-Leon, James R. Blakley	Power-Aware Management in Cloud Data Centers.	CloudCom	2009	DBLP DOI BibTeX RDF	cloud management, virtualization management, energy-proportional computing, power management, power efficiency, power-aware scheduling
5	Jinha Park, Sungjoo Yoo, Sunggu Lee, Chanik Park	Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems.	SEUS	2009	DBLP DOI BibTeX RDF	low power states, measurement, power consumption, dynamic power management, Solid state disk, trace-based simulation
5	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
5	Anshuman Chandra, Rohit Kapur	Bounded Adjacent Fill for Low Capture Power Scan Testing.	VTS	2008	DBLP DOI BibTeX RDF	capture power, random fill, shift power, test, low power, scan
5	Deying Li, Hongwei Du, Wenping Chen	Power conservation for strongly connected topology control in wireless sensor network.	FOWANC	2008	DBLP DOI BibTeX RDF	minimum power topology control, power threshold, wireless sensor networks, greedy algorithm, power assignment
5	Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee	Compilation for compact power-gating controls.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low power, balanced scheduling, power-gating mechanisms, data-flow analysis, leakage-power reduction
5	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti	Variation-Tolerant, Power-Safe Pattern Generation.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	low-power ATPG, process variation, IR drop, peak power, power profiling
5	Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska	Electromigration and voltage drop aware power grid optimization for power gated ICs.	ISLPED	2007	DBLP DOI BibTeX RDF	power supply grid, power gating, electromigration
5	Behnam Amelifard, Massoud Pedram	Design of an efficient power delivery network in an soc to enable dynamic power management.	ISLPED	2007	DBLP DOI BibTeX RDF	power delivery network, voltage regulator, low-power design, DC-DC converter
5	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Timing-driven row-based power gating.	ISLPED	2007	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
5	Keejong Kim, Hamid Mahmoodi, Kaushik Roy	A low-power SRAM using bit-line charge-recycling technique.	ISLPED	2007	DBLP DOI BibTeX RDF	write margin, write power, low power, process variation, SRAM, charge-recycling
5	Bingxue Yao, Yubin Zhong	The Construction of Power Ring.	ICFIE	2007	DBLP DOI BibTeX RDF	HX Rings, Power Ring, Regular Power Ring, Nontrivial HX Ring, Nontrivial Power Ring
5	Mesut E. Baran, Nikhil Mahajan, Sercan Teleke	Simulation-based design of protection schemes for shipboard power systems.	SCSC	2007	DBLP DOI BibTeX RDF	electromagnetic transient analysis, power electronic systems, power system protection, power system simulation
5	Jian Wu, Noel N. Schulz, Wenzhong Gao	Power system load modeling in virtual test bed.	SCSC	2007	DBLP DOI BibTeX RDF	power system dynamic performance, power system modeling, power system simulation, resistive companion model, time domain simulation, load modeling
5	Jorgen Peddersen, Sri Parameswaran	CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time.	ASP-DAC	2007	DBLP DOI BibTeX RDF	dynamic power optimization, CLIPPER, counter-based low impact processor, run-time power optimization, power consumption, energy consumption
5	Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis	Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.	ASP-DAC	2007	DBLP DOI BibTeX RDF	optimum prefix adders, static power consumptions, dynamic power consumptions, high-level synthesis, integer linear programming, buffer insertion, gate sizing, power models, ASIC designs, parallel prefix adder, binary adder
5	Mehdi Hakimi, Seyyed Masoud Moghaddas Tafreshi, M. R. Rajati	Unit Sizing of a Stand-Alone Hybrid Power System Using Model-Free Optimization.	GrC	2007	DBLP DOI BibTeX RDF	reformer, hybrid power system, optimal sizing, particle swarm optimization I. NOMENCLATURE P conv wg - Power delivered from wind turbines to converter (kw) P el wg - Power delivered from wind turbines to electrolyzer (kw) P k el tan - Power delive, K. N. Toosi University of Technology, Tehran-Iran (e-mail: sm_hakimi@yahoo.com). S.M.M.Tafreshi is with the Department of Electrical Engineering, K. N. Toosi University of Technology, Tehran-Iran (e-mail: tafreshi@eetd.kntu.ac.ir). M. R. Rajati is with the Department of Electrical Engineering, K. N. Toosi University of Technology, Tehran-Iran (e-mail: mohammadreza.rajati@gmail.com). P wt Power generated by wind turbines (kw) Pload Load power (kw) E k tan Stored energy in the hydrogen tank (kwh) fc, el, conv Efficiency of fuel cell, electrolyzer, converter NPCindex Net present cost (the index shows the corresponding component) ($) S Single-payment present worth factor R Life time of project (year) L Life time of each components (year) Ir Inter, fuel cell, wind turbine
5	Yi-Ping You, Chingren Lee, Jenq Kuen Lee	Compilers for leakage power reduction.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Compilers for low power, power-gating mechanisms, leakage-power reduction
5	Lijun Gao, Keshab K. Parhi	Models for Architectural Power and Power Grid Noise Analysis on Data Bus.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	augmented DBT model, SCTA model, STCTA model, power consumption, switching activity, power spectrum, transition probability, power grid noise, transition activity
5	Mohammad Sharifkhani, Manoj Sachdev	A low power SRAM architecture based on segmented virtual grounding.	ISLPED	2006	DBLP DOI BibTeX RDF	static-random access memory, write power reduction, low-power, SRAM, leakage reduction
5	Vijay Raghunathan, Pai H. Chou	Design and power management of energy harvesting embedded systems.	ISLPED	2006	DBLP DOI BibTeX RDF	power management, energy harvesting, wireless sensors, solar power
5	Baozhen Yu, Michael L. Bushnell	A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	power cutoff, standby current, stacking, leakage current, dynamic power
5	Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee	A sink-n-hoist framework for leakage power reduction.	EMSOFT	2005	DBLP DOI BibTeX RDF	balanced scheduling, compilers for low power, power-gating mechanisms, data-flow analysis, leakage power reduction
5	Dongsheng Ma, Janet Meiling Wang, Mohankumar N. Somasundaram, Zongqi Hu	Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes.	ISLPED	2005	DBLP DOI BibTeX RDF	dynamic power loss control, wireless sensing node, power efficiency, DC-DC converter, charge pump
5	Jeff Siebert, Jamie Collier, Rajeevan Amirtharajah	Self-timed circuits for energy harvesting AC power supplies.	ISLPED	2005	DBLP DOI BibTeX RDF	AC power supplies, power-on-reset, energy harvesting, self-timed circuits, dynamic memory
5	Gilberto Contreras, Margaret Martonosi	Power prediction for intel XScale processors using performance monitoring unit events.	ISLPED	2005	DBLP DOI BibTeX RDF	XScale, power estimation, power modeling, hardware performance counters
5	Seongmoo Heo, Krste Asanovic	Replacing global wires with an on-chip network: a power analysis.	ISLPED	2005	DBLP DOI BibTeX RDF	on-chip network power model, tile size, wire power model, pipelining, router, tiled architecture
5	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny	On-chip power distribution grids with multiple supply voltages for high performance integrated circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multiple power supply voltages, power distribution grids, decoupling capacitors, power distribution systems
5	Dexin Li, Pai H. Chou	Application/architecture power co-optimization for embedded systems powered by renewable sources.	DAC	2005	DBLP DOI BibTeX RDF	load matching, power utilization, renewable power source, power management, architectural optimization
5	Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang	Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	low-power multiplier, coefficient optimization, power weight factor, power modeling
5	Andrea Bona, Vittorio Zaccaria, Roberto Zafalon	Low Effort, High Accuracy Network-on-Chip Power Macro Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF	Network-on-Chip power analysis, communication based low power design, system-level energy optimization
5	Marco Bucci, Michele Guglielmo, Raimondo Luzzi, Alessandro Trifiletti	A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors.	PATMOS	2004	DBLP DOI BibTeX RDF	chipcards, cryptography, Differential power analysis, DPA, power analysis, countermeasures
5	Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose	Microarchitectural techniques for power gating of execution units.	ISLPED	2004	DBLP DOI BibTeX RDF	execution units, low power, microarchitecture, power-gating
5	Chulsung Park, Pai H. Chou	Power utility maximization for multiple-supply systems by a load-matching switch.	ISLPED	2004	DBLP DOI BibTeX RDF	load matching, solar-aware, power management, power model, solar energy, photovoltaics
5	R. Reed Taylor, Herman Schmit	Creating a power-aware structured ASIC.	ISLPED	2004	DBLP DOI BibTeX RDF	VPGA, low-power, voltage scaling, power optimization, gate sizing, structured ASIC
5	Vittorio Ricchiuti	Power Bus Signal Integrity Improvement and EMI Mitigation on Multilayer High-Speed Digital PCBs with Embedded Capacitance.	IEEE Trans. Mob. Comput.	2003	DBLP DOI BibTeX RDF	Embedded capacitance, power bus, power/ground layers, power supply decoupling, electric field strength, S-parameters
5	Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu	Reducing Average and Peak Test Power Through Scan Chain Modification.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	test power reduction, scan chain modification, average test power, peak test power, scan testing
5	Xuning Chen, Li-Shiuan Peh	Leakage power modeling and optimization in interconnection networks.	ISLPED	2003	DBLP DOI BibTeX RDF	interconnection networks, leakage power, power optimization
5	Deming Chen, Jason Cong, Yiping Fan	Low-power high-level synthesis for FPGA architectures.	ISLPED	2003	DBLP DOI BibTeX RDF	FPGA power reduction, RT-level power estimation, data path optimization
5	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai	A power-aware SWDR cell for reducing cache write power.	ISLPED	2003	DBLP DOI BibTeX RDF	circuit-level, write power, low power, cache, SRAM
5	Andreas Moshovos	Checkpointing alternatives for high performance, power-aware processors.	ISLPED	2003	DBLP DOI BibTeX RDF	checkpointing, power-aware, out-of-order execution, renaming, power density
5	Kaveh Shakeri, James D. Meindl	Temperature Variable Supply Voltage for Power Reduction.	ISVLSI	2002	DBLP DOI BibTeX RDF	CMOS, Temperature, Power reduction, Dynamic Power, MOSFET, Static Power
5	David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin	Impact of Technology Scaling in the Clock System Power.	ISVLSI	2002	DBLP DOI BibTeX RDF	Clock Power, Low-power-design, Power modeling, Technology Scaling
5	William C. Athas, Lynn Youngs, Andrew Reinhart	Compact models for estimating microprocessor frequency and power.	ISLPED	2002	DBLP DOI BibTeX RDF	VLSI, low-power, microprocessors, ASIC, power estimation, curve-fitting, delay modeling
5	Kyu-won Choi, Abhijit Chatterjee	HA2TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI.	ISLPED	2002	DBLP DOI BibTeX RDF	gate-level power optimization, time slack distribution, low-power design
5	Rita Yu Chen, Mary Jane Irwin, Raminder Singh Bajwa	Architecture-level power estimation and design experiments.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	architecture tradeoff, architecture-level power estimation, control unit, energy table, instruction format transition, output signal transition, power analysis and estimation, switch capacitance, low power design, hardware/software codesign, energy model, functional unit, computer-aided design of VLSI
5	Fei Li, Lei He	Maximum current estimation considering power gating.	ISPD	2001	DBLP DOI BibTeX RDF	low-power design, ATPG, power estimation, power gating
5	Khalil Najafi	Low-power micromachined microsystems (invited talk).	ISLPED	2000	DBLP DOI BibTeX RDF	micromachining, power sources, low-power, MEMS, energy harvesting, microsystems
5	Kavel M. Büyüksahin, Farid N. Najm	High-level power estimation with interconnect effects.	ISLPED	2000	DBLP DOI BibTeX RDF	high-level power estimation, interconnect capacitance estimation, register transfer level (RTL) power estimation
5	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
5	Xiaodong Zhang, Kaushik Roy	Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	BIST Synthesis, Weighted Random Pattern Generator, Low Power BIST, Testing, Low Power, Cellular Automata, Peak Power
5	Michael Benoit, Sandy Taylor, David Overhauser, Steffen Rochel	Power distribution in high-performance design.	ISLPED	1998	DBLP DOI BibTeX RDF	power grid, IR drop, power distribution
5	Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano	Power invariant vector compaction based on bit clustering and temporal partitioning.	ISLPED	1998	DBLP DOI BibTeX RDF	low power VLSI design, vector compaction, Markov chains, power estimation
5	Atila Alvandpour, Per Larsson-Edefors, Christer Svensson	Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.	ISLPED	1998	DBLP DOI BibTeX RDF	short-circuit current, power consumption, power estimation
5	David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards	Emerging power management tools for processor design.	ISLPED	1998	DBLP DOI BibTeX RDF	low power CAD, standby leakage, power distribution
5	Zhanping Chen, Kaushik Roy, Tan-Li Chou	Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.	ICCAD	1997	DBLP DOI BibTeX RDF	Monte Carlo based approach, maximum bounds, minimum bounds, power dissipation estimation, power sensitivity, primary inputs, signal properties, signal switching, uncertain specifications, logic CAD, CMOS logic circuits, power estimation, CMOS circuits, signal probability, statistical technique
5	Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou	A power modeling and characterization method for macrocells using structure information.	ICCAD	1997	DBLP DOI BibTeX RDF	Power modeling for macrocells, RTL power estimations, State transition graph and Power characterization