Search results for "power and performance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Allan Hartstein, Thomas R. Puzak	The optimum pipeline depth considering both power and performance.	TACO	2004	DBLP DOI BibTeX RDF	Pipeline Depth, Power and Performance, Workload Specificity, Simulation
2	Sunpyo Hong, Hyesoon Kim	An integrated GPU power and performance model.	ISCA	2010	DBLP DOI BibTeX RDF	GPU architecture, performance, energy, analytical model, CUDA, power estimation
2	Vinicius Petrucci, Orlando Loques, Daniel Mossé	Dynamic optimization of power and performance for virtualized server clusters.	SAC	2010	DBLP DOI BibTeX RDF	virtualization, power optimization, server clusters
2	Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw	A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Bithika Khargharia, Salim Hariri, Mazin S. Yousif	Autonomic power and performance management for computing systems.	Cluster Computing	2008	DBLP DOI BibTeX RDF	Optimization, Power, Autonomic management
2	Sheng-Chih Lin, Kaustav Banerjee	A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Mahmoud Ben Naser, Csaba Andras Moritz	Power and performance tradeoffs with process variation resilient adaptive cache architectures.	SBCCI	2008	DBLP DOI BibTeX RDF	process variations, leakage power, adaptive cache
2	Toshinori Sato, Toshimasa Funaki	Dependability, power, and performance trade-off on a multicore processor.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Giovanni Beltrame, Donatella Sciuto, Cristina Silvano	Multi-Accuracy Power and Performance Transaction-Level Modeling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Mahdiar Hosein Ghadiry, Mahdieh Nadi Senjani, M. T. Manzuri-Shalmani, Dara Rahmati	Effect of number of faults on NoC power and performance.	ICPADS	2007	DBLP DOI BibTeX RDF
2	Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran	ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Manho Kim, Daewook Kim, Gerald E. Sobelman	Network-on-chip link analysis under power and performance constraints.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Clint W. Smullen, Tarek M. Taha	PSATSim: an interactive graphical superscalar architecture simulator for power and performance analysis.	WCAE	2006	DBLP DOI BibTeX RDF
2	Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan	Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	performance optimization, power modeling, Motion estimation algorithm
2	Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director	Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.	DAC	2005	DBLP DOI BibTeX RDF	correlation, variability, yield, leakage
2	Victor V. Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma	Integrated Analysis of Power and Performance for Pipelined Microprocessors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
2	Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma	Optimizing pipelines for power and performance.	MICRO	2002	DBLP DOI BibTeX RDF
2	Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee	PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations.	CASES	2002	DBLP DOI BibTeX RDF	FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization
2	Afzal Malik, Bill Moyer, Roger Zhou	Embedded cache architecture with programmable write buffer support for power and performance flexibility.	CASES	2002	DBLP DOI BibTeX RDF	cache control, copyback, push buffer, writethrough, programmable, cache management, write buffer
2	David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn	Managing power and performance for System-on-Chip designs using Voltage Islands.	ICCAD	2002	DBLP DOI BibTeX RDF
2	David Brooks, Margaret Martonosi	Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance.	ACM Trans. Comput. Syst.	2000	DBLP DOI BibTeX RDF
2	Afzal Malik, Bill Moyer, Dan Cermak	A low power unified cache architecture providing power and performance flexibility (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
1	Ehsan Totoni, Babak Behzad, Swapnil Ghike, Josep Torrellas	Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs.	ISPASS	2012	DBLP DOI BibTeX RDF
1	Muhammad Faisal Iqbal, Lizy K. John	Power and performance analysis of network traffic prediction techniques.	ISPASS	2012	DBLP DOI BibTeX RDF
1	Anita Tino, Gul N. Khan	Designing power and performance optimal application-specific Network-on-Chip architectures.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Nikolas Kroupis, Dimitrios Soudris	FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Dara Kusic, Nagarajan Kandasamy, Guofei Jiang	Combined Power and Performance Management of Virtualized Computing Environments Serving Session-Based Workloads.	IEEE Transactions on Network and Service Management	2011	DBLP DOI BibTeX RDF
1	Dmytro Dyachuk, Michele Mazzucco	On Allocation Policies for Power and Performance	CoRR	2011	DBLP BibTeX RDF
1	Christian Schuck, Bastian Haetzer, Jürgen Becker	Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs.	Int. J. Reconfig. Comp.	2011	DBLP DOI BibTeX RDF
1	Palden Lama, Xiaobo Zhou	PERFUME: Power and performance guarantee with fuzzy MIMO control in virtualized servers.	IWQoS	2011	DBLP DOI BibTeX RDF
1	Vinicius Petrucci, Enrique V. Carrera, Orlando Loques, Julius C. B. Leite, Daniel Mossé	Optimized Management of Power and Performance for Virtualized Heterogeneous Server Clusters.	CCGRID	2011	DBLP DOI BibTeX RDF
1	Kaiqi Xiong	Power and Performance Management in Priority-Type Cluster Computing Systems.	IPDPS	2011	DBLP DOI BibTeX RDF
1	Seung Eun Lee	Cycle Accurate Power and Performance Simulator for Design Space Exploration on a Many-Core Platform.	CSEE	2011	DBLP DOI BibTeX RDF
1	Florian Thoma, Michael Hübner, Diana Göhringer, Hasam Ümitcan Yilmaz, Jürgen Becker	Power and performance optimization through MPI supported dynamic voltage and frequency scaling.	MARC Symposium	2011	DBLP BibTeX RDF
1	Eman Copty, Gila Kamhi, Sasha Novakovsky	Transaction level statistical analysis for efficient micro-architectural power and performance studies.	DAC	2011	DBLP DOI BibTeX RDF
1	Zheng Li, Moustafa Mohamed, Xi Chen, Alan Rolf Mickelson, Li Shang	Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance.	DAC	2011	DBLP DOI BibTeX RDF
1	Martin Streubühr, Rafael Rosales, Ralph Hasholzner, Christian Haubelt, Jürgen Teich	ESL power and performance estimation for heterogeneous MPSOCS using SystemC.	FDL	2011	DBLP BibTeX RDF
1	Yongqiang Gao, Zhengwei Qi, Yubin Wu, Rui Wang, Liang Liu, Jitao Xu, Haibing Guan	A Power and Performance Management Framework for Virtualized Server Clusters.	GreenCom	2011	DBLP DOI BibTeX RDF
1	Mohsen Sharifi, Mahsa Najafzadeh, Hadi Salimi	Co-management of Power and Performance in Virtualized Distributed Environments.	GPC	2011	DBLP DOI BibTeX RDF
1	Changshu Zhang, Arun Ravindran, Kushal Datta, Arindam Mukherjee, Bharat Joshi	A machine learning approach to modeling power and performance of chip multiprocessors.	ICCD	2011	DBLP DOI BibTeX RDF
1	Matthias Kühnle, Alisson Vasconcelos De Brito, Christoph Roth, Matthias Krüsselin, Jürgen Becker	An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Luciano Bertini, Julius C. B. Leite, Daniel Mossé	Power and performance control of soft real-time web server clusters.	Inf. Process. Lett.	2010	DBLP DOI BibTeX RDF
1	Reza Zamani, Ahmad Afsahi	Adaptive estimation and prediction of power and performance in high performance computing.	Computer Science - R&D	2010	DBLP DOI BibTeX RDF
1	Hongzhong Zheng, Zhichun Zhu	Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	DRAM systems, performance, power, Multicore processors
1	Jiayu Gong, Cheng-Zhong Xu	vPnP: Automated coordination of power and performance in virtualized datacenters.	IWQoS	2010	DBLP DOI BibTeX RDF
1	Xunteng Xu, Lin Gu, Jianping Wang, Guoliang Xing	Negotiate power and performance in the reality of RFID systems.	PerCom	2010	DBLP DOI BibTeX RDF
1	Abhijit Chatterjee	Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performance.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs)
1	Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan	Optimizing power and performance for reliable on-chip networks.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Alma Riska, Evgenia Smirni	Autonomic exploration of trade-offs between power and performance in disk drives.	ICAC	2010	DBLP DOI BibTeX RDF
1	Krisztián Flautner	Optimize your power and performance yields and regain those sleepless nights.	DATE	2010	DBLP BibTeX RDF
1	Khalid Latif 0002, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen	Power- and performance-aware IP mapping for NoC-based MPSoC platforms.	ICECS	2010	DBLP DOI BibTeX RDF
1	Dmytro Dyachuk, Michele Mazzucco	On allocation policies for power and performance.	GRID	2010	DBLP DOI BibTeX RDF
1	Vinicius Petrucci, Orlando Loques, Daniel Mossé	A dynamic optimization model for power and performance management of virtualized clusters.	e-Energy	2010	DBLP DOI BibTeX RDF
1	Anita Tino, Gul N. Khan	Power and Performance Tabu Search Based Multicore Network-on-Chip Design.	ICPP Workshops	2010	DBLP DOI BibTeX RDF
1	Massoud Pedram, Inkwon Hwang	Power and Performance Modeling in a Virtualized Server System.	ICPP Workshops	2010	DBLP DOI BibTeX RDF
1	Meikel Poess, Raghunath Othayoth Nambiar	A power consumption analysis of decision support systems.	WOSP/SIPEW	2010	DBLP DOI BibTeX RDF	performance tuning and optimization, power and performance, use of benchmarks in industry and academia, energy efficiency, benchmarking, software performance testing
1	Jason Cong, Chunyue Liu, Glenn Reinman	ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip.	DAC	2010	DBLP DOI BibTeX RDF	application-specific Network-on-Chip, deadlock-free routing
1	Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol	An efficient dynamically reconfigurable on-chip network architecture.	DAC	2010	DBLP DOI BibTeX RDF	performance, reconfigurable, topology, power, NoC
1	Amith Singhee, Pamela Castalino	Pareto sampling: choosing the right weights by derivative pursuit.	DAC	2010	DBLP DOI BibTeX RDF	derivative pursuit, multi-objective optimization, tradeoff, Pareto
1	Dennis Abts, Michael R. Marty, Philip M. Wells, Peter Klausler, Hong Liu	Energy proportional datacenter networks.	ISCA	2010	DBLP DOI BibTeX RDF	datacenter networks, low-power networking, interconnection networks
1	Gaurav Dhiman, Vasileios Kontorinis, Dean M. Tullsen, Tajana Rosing, Eric Saxe, Jonathan Chew	Dynamic workload characterization for power efficient scheduling on CMP systems.	ISLPED	2010	DBLP DOI BibTeX RDF	power, multi-cores, workload characterization
1	Dara Kusic, Jeffrey O. Kephart, James E. Hanson, Nagarajan Kandasamy, Guofei Jiang	Power and performance management of virtualized computing environments via lookahead control.	Cluster Computing	2009	DBLP DOI BibTeX RDF
1	Sebastian Herbert, Diana Marculescu	Mitigating the Impact of Variability on Chip-Multiprocessor Power and Performance.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Alma Riska, Ningfang Mi, Evgenia Smirni, Giuliano Casale	Feasibility regions: exploiting tradeoffs between power and performance in disk drives.	SIGMETRICS Performance Evaluation Review	2009	DBLP DOI BibTeX RDF
1	Osamu Takahashi, Michael Seningen	Nanoscale power and performance optimizations.	CICC	2009	DBLP DOI BibTeX RDF
1	Andrzej Kochut	Power and performance modeling of virtualized desktop systems.	MASCOTS	2009	DBLP DOI BibTeX RDF
1	Raid Ayoub, Alex Orailoglu	Filtering Global History: Power and Performance Efficient Branch Predictor.	ASAP	2009	DBLP DOI BibTeX RDF
1	Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur	Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Jian Li, Lixin Zhang 0002, Evan Speight, Yuan Xie	Power and performance of read-write aware Hybrid Caches with non-volatile memories.	DATE	2009	DBLP BibTeX RDF
1	Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Jun Yang 0002, Li Zhao	Frequent value compression in packet-based NoC architectures.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak	Exploiting residue number system for power-efficient digital signal processing in embedded processors.	CASES	2009	DBLP DOI BibTeX RDF	compiler, power, processor, residue number system, per-
1	Emre Tuncer, Jordi Cortadella, Luciano Lavagno	Enabling adaptability through elastic clocks.	DAC	2009	DBLP DOI BibTeX RDF	low power design, GALS, desynchronization, adaptive voltage scaling
1	David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan	Architectural enhancements in Stratix-IIITM and Stratix-IVTM.	FPGA	2009	DBLP DOI BibTeX RDF	power management, memory, fpga architecture, static power
1	Krishna K. Rangan, Gu-Yeon Wei, David Brooks	Thread motion: fine-grained power management for multi-core systems.	ISCA	2009	DBLP DOI BibTeX RDF	multi-core power management, thread motion, dvfs
1	Xiaoxia Wu, Jian Li, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
1	Gaurav Dhiman, Giacomo Marchetti, Tajana Rosing	vGreen: a system for energy efficient computing in virtualized environments.	ISLPED	2009	DBLP DOI BibTeX RDF	virtualization, energy, migration, workload characterization
1	Kevin Zhang	Circuit design in nano-scale CMOS era: opportunities & challenges.	ISLPED	2009	DBLP DOI BibTeX RDF	VLSI, CMOS, circuit
1	Vinicius Petrucci, Orlando Loques, Daniel Mossé	A framework for dynamic adaptation of power-aware server clusters.	SAC	2009	DBLP DOI BibTeX RDF	framework, power management, dynamic adaptation, server clusters
1	Sebastian Herbert, Diana Marculescu	Variation-aware dynamic voltage/frequency scaling.	HPCA	2009	DBLP DOI BibTeX RDF
1	Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell	Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.	HPCA	2009	DBLP DOI BibTeX RDF
1	Min Yeol Lim, Freeman L. Rawson III, Tyler K. Bletsch, Vincent W. Freeh	PADD: Power Aware Domain Distribution.	ICDCS	2009	DBLP DOI BibTeX RDF
1	Xiaoke Qin, Prabhat Mishra	Efficient Placement of Compressed Code for Parallel Decompression.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar	WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Klaus-Dieter Lange	Identifying Shades of Green: The SPECpower Benchmarks.	IEEE Computer	2009	DBLP DOI BibTeX RDF
1	Bithika Khargharia, Salim Hariri, Mazin S. Yousif	An Adaptive Interleaving Technique for Memory Performance-per-Watt Management.	IEEE Trans. Parallel Distrib. Syst.	2009	DBLP DOI BibTeX RDF
1	Ruey-Song Huang, Tzyy-Ping Jung, Scott Makeig	Tonic Changes in EEG Power Spectra during Simulated Driving.	HCI	2009	DBLP DOI BibTeX RDF	ICA, EEG, driving, alertness, alpha, delta, reaction time, theta
1	Ali Ahmadinia, Tughrul Arslan, Hernando Fernandez-Canque	Optimization of Reconfigurable Multi-core SOCs for Multi-standard Applications.	KES	2009	DBLP DOI BibTeX RDF
1	Xinqi Wang, Tevfik Kosar	Design and Implementation of Metadata System in PetaShare.	SSDBM	2009	DBLP DOI BibTeX RDF	Protege, PetaShare, Ontology, Metadata, Data Intensive Computing, iRODS
1	Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri	Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Subhasis Banerjee, G. Surendra, S. K. Nandy	On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation.	Journal of Systems Architecture - Embedded Systems Design	2008	DBLP DOI BibTeX RDF
1	Yen-Jen Chang, Yuan-Hong Liao	Hybrid-Type CAM Design for Both Power and Performance Efficiency.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Joris Slegers, Nigel Thomas, Isi Mitrani	Dynamic Server Allocation for Power and Performance.	SIPEW	2008	DBLP DOI BibTeX RDF	Resource allocation, dynamic optimization, power conservation
1	Ahmed Abdallah, Wayne Wolf, Graham R. Hellestrand	Using Empirical Science to Engineer Systems: Optimizing Cache for Power and Performance.	DSD	2008	DBLP DOI BibTeX RDF
1	Bithika Khargharia, Salim Hariri, Wael Kdouh, Manal Houri, Hesham El-Rewini, Mazin S. Yousif	Autonomic power and performance management of high-performance servers.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Clinton Wills Smullen IV, Shahrukh Rohinton Tarapore, Sudhanva Gurumurthi, Parthasarathy Ranganathan, Mustafa Uysal	Active storage revisited: the case for power and performance benefits for unstructured data processing applications.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	performance, power, unstructured data, active storage
1	Dara Kusic, Jeffrey O. Kephart, James E. Hanson, Nagarajan Kandasamy, Guofei Jiang	Power and Performance Management of Virtualized Computing Environments Via Lookahead Control.	ICAC	2008	DBLP DOI BibTeX RDF
1	Rajarshi Das, Jeffrey O. Kephart, Charles Lefurgy, Gerald Tesauro, David W. Levine, Hoi Chan	Autonomic multi-agent management of power and performance in data centers.	AAMAS (Industry Track)	2008	DBLP DOI BibTeX RDF
1	Kyle O'Brien, David Salyers, Aaron Striegel, Christian Poellabauer	Power and performance characteristics of USB flash drives.	WOWMOM	2008	DBLP DOI BibTeX RDF
1	Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-Hsin S. Lee	Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	MESI protocol, internal and external snoops, self-modifying code, chip multiprocessors