Search results for "power dissipation reduction"

Found 13 publication records. Showing 13 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	Efficient partial scan cell gating for low-power scan-based testing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	partial gating, scan cell gating, Low-power testing, scan-based testing
1	Ahmed Shebaita, Yehea I. Ismail	Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Yuantao Peng, Xun Liu	Low-power repeater insertion with both delay and slew rate constraints.	DAC	2006	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion, slew rate
1	Ireneusz Brzozowski, Andrzej Kos	Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Alexander Fish, Shy Hamami, Orly Yadid-Pecht	Self-powered active pixel sensors for ultra low-power applications.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Konstantina Karagianni, Vassilis Paliouras	Low-Power Aspects of Nonlinear Signal Processing.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi	Power Dissipation Reductions with Genetic Algorithms.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
1	Mauro Olivieri	Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Abdoul Rjoub, M. Alrousan, O. Jarrah, Odysseas G. Koufopavlou	Multi-level low swing voltage values for low power design applications.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Antonio G. M. Strollo, Ettore Napoli, Davide De Caro	New clock-gating techniques for low-power flip-flops.	ISLPED	2000	DBLP DOI BibTeX RDF	flip-fops, CMOS digital integrated circuits, transition probability, low-power circuits
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Low power realization of FIR filters using multirate architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips
1	José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh	Optimization of combinational and sequential logic circuits for low power using precomputation.	ARVLSI	1995	DBLP DOI BibTeX RDF	sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle
1	Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou	Precomputation-based sequential logic optimization for low power.	IEEE Trans. VLSI Syst.	1994	DBLP DOI BibTeX RDF