Search results for "power estimation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Axel Reimer, Arne Schulz, Wolfgang Nebel	Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs.	ISLPED	2006	DBLP DOI BibTeX RDF	FPGA power estimation, RT-level power modeling, high-level power estimation
4	Kavel M. Büyüksahin, Farid N. Najm	High-level power estimation with interconnect effects.	ISLPED	2000	DBLP DOI BibTeX RDF	high-level power estimation, interconnect capacitance estimation, register transfer level (RTL) power estimation
3	Feng Liu, QingPing Tan, Xiaoyu Song, Naeem Abbasi	AOP-based high-level power estimation in SystemC.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	systemc, power estimation, aspectc++
3	Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos	A multi-model power estimation engine for accuracy optimization.	ISLPED	2007	DBLP DOI BibTeX RDF	power macromodeling, powerSC, low power design, systemC, power estimation
3	Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas	Probabilistic gate-level power estimation using a novel waveform set method.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	probabilistic power estimation, probability waveform, transition density, combinational logic, gate-level
3	Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung	Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	IPI power model, black-box power model, prefetch power model, processor power modeling, software power estimation
3	Fei Hu, Vishwani D. Agrawal	Dual-transition glitch filtering in probabilistic waveform power estimation.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	dual-transition probability, dynamic power estimation, glitch filtering, probabilistic waveform simulation
3	Joel Coburn, Srivaths Ravi, Anand Raghunathan	Power emulation: a new paradigm for power estimation.	DAC	2005	DBLP DOI BibTeX RDF	simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels
3	Michael Eiermann, Walter Stechele	Novel modeling techniques for RTL power estimation.	ISLPED	2002	DBLP DOI BibTeX RDF	RTL macromodels, low power, power estimation, power modeling
3	Rita Yu Chen, Mary Jane Irwin, Raminder Singh Bajwa	Architecture-level power estimation and design experiments.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	architecture tradeoff, architecture-level power estimation, control unit, energy table, instruction format transition, output signal transition, power analysis and estimation, switch capacitance, low power design, hardware/software codesign, energy model, functional unit, computer-aided design of VLSI
3	Gerald Kaefer, Josef Haid, Bernd Hofer, Gerhard Schall, Reinhold Weiss	Framework for Power Aware Remote Processing: Design and Implementation of a Dynamic Power Estimation Unit.	ISWC	2001	DBLP DOI BibTeX RDF	remote processing, wireless communication, power estimation, power awareness, code migration
3	Ricardo Ferreira, A.-M. Trullemans, José C. Costa, José Monteiro	Probabilistic Bottom-Up RTL Power Estimation.	ISQED	2000	DBLP DOI BibTeX RDF	Register Tranfers Level, Power Estimation, Glitches, ZBDD
3	Muhammad M. Khellah, Mohamed I. Elmasry	Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	low-power design, power estimation, high-level design
3	Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino	Power Estimation of Behavioral Descriptions.	DATE	1998	DBLP DOI BibTeX RDF	Behavioral power estimation, macromodeling, design exploration
3	Chuan-Yu Wang, Kaushik Roy	COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	CMOS Digital Circuits, Reliability, Power Estimation
3	Daniel Brand, Chandramouli Visweswariah	Inaccuracies in power estimation during logic synthesis.	ICCAD	1996	DBLP DOI BibTeX RDF	glitch power, simulation, logic synthesis, power estimation, power optimization
3	Farid N. Najm	Power estimation techniques for integrated circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	power estimation VLSI circuit survey tutorial probability statistics
2	Swapna R. Dontharaju, Shen Chih Tung, James T. Cain, Leonid Mats, Marlin H. Mickle, Alex K. Jones	A design automation and power estimation flow for RFID systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	low-power, RFID, prototyping, design automation
2	Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar	Power estimation methodology for a high-level synthesis framework.	ISQED	2009	DBLP DOI BibTeX RDF
2	Sriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham	Functionally valid gate-level peak power estimation for processors.	ISQED	2009	DBLP DOI BibTeX RDF
2	Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsin Chang	A novel ACO-based pattern generation for peak power estimation in VLSI circuits.	ISQED	2009	DBLP DOI BibTeX RDF
2	Luciano Ost, Guilherme Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp, Fernando Moraes	A high abstraction, high accuracy power estimation model for networks-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	high abstraction modeling, networks-on-chip, power modeling
2	Babak Hidaji, Mohamad Reza Andalibizadeh, Salar Alipour	Micro-architectural power estimation and optimization.	EIT	2009	DBLP DOI BibTeX RDF
2	Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic	Floorplan-based FPGA interconnect power estimation in DSP circuits.	SLIP	2009	DBLP DOI BibTeX RDF	fpga, low power, interconnects, power estimation
2	Karan Singh, Major Bhadauria, Sally A. McKee	Prediction-based power estimation and scheduling for CMPs.	ICS	2009	DBLP DOI BibTeX RDF	power estimation, performance counters
2	Miriam Allalouf, Yuriy Arbitman, Michael Factor, Ronen I. Kat, Kalman Z. Meth, Dalit Naor	Storage modeling for power estimation.	SYSTOR	2009	DBLP DOI BibTeX RDF	modeling, power, storage
2	Sören Sonntag, Wenjian Wang	Area and power consumption estimations at system level with SystemQ 2.0.	SimuTools	2009	DBLP DOI BibTeX RDF	SystemQ, area and power estimation, modeling, synthesis, electronic system level
2	Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi	System-level PVT variation-aware power exploration of on-chip communication architectures.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	PVT variation, on-chip communication architectures, performance exploration, high-level synthesis, power estimation, digital systems
2	Ivan Wang Hei Ho, Bongjun Ko, Murtaza Zafer, Chatschik Bisdikian, Kin K. Leung	Cooperative Transmit-Power Estimation in MANETs.	WCNC	2008	DBLP DOI BibTeX RDF
2	Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri	A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Ruzica Jevtic, Carlos Carreras, Domenik Helms	A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components.	ReConFig	2008	DBLP DOI BibTeX RDF	FPGA, low power, power estimation, high-level modelling
2	Youngjin Cho, Younghyun Kim, Sangyoung Park, Naehyuck Chang	System-level power estimation using an on-chip bus performance monitoring unit.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Murtaza Zafer, Bongjun Ko, Ivan Wang Hei Ho	Cooperative transmit-power estimation under wireless fading.	MobiHoc	2008	DBLP DOI BibTeX RDF	cooperative monitoring, sensor network, mobile ad-hoc network, wireless, maximum likelihood, power estimation
2	Shilpa Bhoj, Dinesh Bhatia	Early stage FPGA interconnect leakage power estimation.	ICCD	2008	DBLP DOI BibTeX RDF
2	Jian Li, Yao Xie, Petre Stoica, Xiayu Zheng, James Ward	Beampattern Synthesis via a Matrix Approach for Signal Power Estimation.	IEEE Transactions on Signal Processing	2007	DBLP DOI BibTeX RDF
2	Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson	Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.	ISQED	2007	DBLP DOI BibTeX RDF
2	Shilpa Bhoj, Dinesh Bhatia	Pre-route Interconnect Capacitance and Power Estimation in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
2	Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram	A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram	A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits.	PATMOS	2007	DBLP DOI BibTeX RDF
2	William Lloyd Bircher, Lizy K. John	Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events.	ISPASS	2007	DBLP DOI BibTeX RDF	power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model
2	Minh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis	High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process.	DSD	2007	DBLP DOI BibTeX RDF
2	Prashant Agrawal, R. Srinivasa, Ajit N. Oke, Saurabh Vijay	A path based modeling approach for dynamic power estimation.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	thermal design power, power modeling
2	Ying-Wen Bai, Yung-Sen Cheng, Cheng-Hung Tsai	An Approximate Analysis of the Balance among Performance, Utilization and Power Estimation of Server Systems by Use of the Batch Service.	ICON	2007	DBLP DOI BibTeX RDF
2	Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan	Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.	DAC	2007	DBLP DOI BibTeX RDF
2	Yu-Shiang Lin, Dennis Sylvester	Runtime leakage power estimation technique for combinational circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	subthreshold leakage analysis, runtime leakage power estimation technique, dynamic estimation methods, static estimation methods, combinational circuits, error estimation, SPICE simulations
2	José A. de Holanda, Jecel Assumpcao, Denis F. Wolf, Eduardo Marques, João M. P. Cardoso	On Adapting Power Estimation Models for Embedded Soft-Core Processors.	SIES	2007	DBLP DOI BibTeX RDF
2	Fatih Onur Hocaoglu, Mehmet Kurban	The Effect of Missing Wind Speed Data on Wind Power Estimation.	IDEAL	2007	DBLP DOI BibTeX RDF
2	Yongpan Liu, Robert P. Dick, Li Shang, Huazhong Yang	Accurate temperature-dependent integrated circuit leakage power estimation is easy.	DATE	2007	DBLP DOI BibTeX RDF
2	Prakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan	Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena	Switching Activity Models for Power Estimation in FPGA Multipliers.	ARC	2007	DBLP DOI BibTeX RDF
2	Dam Sunwoo, Hassan Al-Sukhni, Jim Holt, Derek Chiou	Early Models for System-Level Power Estimation.	MTV	2007	DBLP DOI BibTeX RDF
2	Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla, Ajit Dingankar	Assertion-Based Modal Power Estimation.	MTV	2007	DBLP DOI BibTeX RDF
2	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt	System level power estimation methodology with H.264 decoder prediction IP case study.	ICCD	2007	DBLP DOI BibTeX RDF
2	Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	RTL-Aware Cycle-Accurate Functional Power Estimation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Elias Todorovich, Eduardo I. Boemo	A-B Nodes Classification for Power Estimation.	FPL	2006	DBLP DOI BibTeX RDF
2	Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri	Delay Constrained Register Transfer Level Dynamic Power Estimation.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Wei Qiang, Yang Cao, Yuan-yuan Yan, Xun Gao	Power Estimation of CMOS Circuits by Neural Network Macromodel.	ISNN	2006	DBLP DOI BibTeX RDF
2	Xiangyuan Liu, Shuming Chen	Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	low-swing interconnect, delay, power, estimation model
2	Wei Wu, Lingling Jin, Jun Yang 0002, Pu Liu, Sheldon X.-D. Tan	A systematic method for functional unit power estimation in microprocessors.	DAC	2006	DBLP DOI BibTeX RDF	microprocessor, power estimation, performance counter
2	Masafumi Onouchi, Tetsuya Yamada, Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine	A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong	A cycle accurate power estimation tool.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo	PowerViP: Soc power estimation framework at transaction level.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Sheng-Chih Lin, Kaustav Banerjee	An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou	A timing dependent power estimation framework considering coupling.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey	Considering process variations during system-level power analysis.	ISLPED	2006	DBLP DOI BibTeX RDF	system-on-chip, low power design, process variations, power analysis, power estimation
2	Xun Liu, Marios C. Papaefthymiou	HyPE: hybrid power estimation for IP-based systems-on-chip.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Kavel M. Büyüksahin, Farid N. Najm	Early power estimation for VLSI circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	W. W. Bachmann, Sorin A. Huss	Efficient algorithms for multilevel power estimation of VLSI circuits.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel	A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang	Power estimation starategies for a low-power security processor.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Yongjun Xu, Jinghua Chen, Zuying Luo, Xiaowei Li	Vector extraction for average total power estimation.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar	Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Joel Coburn, Srivaths Ravi, Anand Raghunathan	Hardware Accelerated Power Estimation.	DATE	2005	DBLP DOI BibTeX RDF
2	Yuichi Nakamura, Takeshi Yoshimura	A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysis.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Fei Hu, Vishwani D. Agrawal	Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
2	Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan	A power estimation methodology for systemC transaction level models.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	CoreConnect, systemC, power analysis, transaction level models, PowerPC
2	Gilberto Contreras, Margaret Martonosi	Power prediction for intel XScale processors using performance monitoring unit events.	ISLPED	2005	DBLP DOI BibTeX RDF	XScale, power estimation, power modeling, hardware performance counters
2	Jason Helge Anderson, Farid N. Najm	Power estimation techniques for FPGAs.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Imed Ben Dhaou, Hannu Tenhunen	Efficient library characterization for high-level power estimation.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Enrico Macii	RTL power estimation and optimization.	SBCCI	2004	DBLP DOI BibTeX RDF
2	Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee	Macro-models for high level area and power estimation on FPGAs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	model, FPGA, high-level synthesis, power estimation, RTL, area estimation
2	Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Power estimation for cycle-accurate functional descriptions of hardware.	ICCAD	2004	DBLP DOI BibTeX RDF
2	Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir	Analytical models for leakage power estimation of memory array structures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	estimation, SRAMs, leakage power
2	Ashok K. Murugavel, N. Ranganathan	Petri net modeling of gate and interconnect delays for power estimation.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Puneet Gupta, Andrew B. Kahng	Quantifying Error in Dynamic Power Estimation of CMOS Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
2	B. Arts, N. van der Eng, Marc J. M. Heijligers, H. Munk, Frans Theeuwen, Luca Benini, Enrico Macii, A. Milia, Roberto Maro, A. Bellu	Statistical Power Estimation of Behavioral Descriptions.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Jürgen Becker, Michael Hübner, Michael Ullmann	Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations.	SBCCI	2003	DBLP DOI BibTeX RDF	Virtex FPGA, runtime reconfiguration, power consumption
2	Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar	Efficient RTL Power Estimation for Large Designs.	VLSI Design	2003	DBLP DOI BibTeX RDF
2	Ana T. Freitas, Arlindo L. Oliveira	Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation.	DATE	2003	DBLP DOI BibTeX RDF
2	Kavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm	ESTIMA: an architectural-level power estimator for multi-ported pipelined register files.	ISLPED	2003	DBLP DOI BibTeX RDF	power estimation, register files, area estimation
2	Deming Chen, Jason Cong, Yiping Fan	Low-power high-level synthesis for FPGA architectures.	ISLPED	2003	DBLP DOI BibTeX RDF	FPGA power reduction, RT-level power estimation, data path optimization
2	Ali Pinar, C. L. Liu	Compacting sequences with invariant transition frequencies.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Sequence compaction, graph algorithms, power estimation
2	Nestoras E. Evmorfopoulos, Georgios I. Stamoulis, John N. Avaritsiotis	A Monte Carlo approach for maximum power estimation based onextreme value theory.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Erik Lauwers, Georges G. E. Gielen	Power estimation methods for analog circuits for architectural exploration of integrated systems.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
2	Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno	Cosimulation-based power estimation for system-on-chip design.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
2	Ashok K. Murugavel, N. Ranganathan	Petri net modeling of gate and interconnect delays for power estimation.	DAC	2002	DBLP DOI BibTeX RDF
2	Sanjay V. Rajopadhye, Steven Derrien	Energy/Power Estimation of Regular Processor Arrays.	ISSS	2002	DBLP DOI BibTeX RDF	processor array partitioning, design space exploration, power estimation, programmable logic
2	Rahul Kumar, C. P. Ravikumar	Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment.	VLSI Design	2002	DBLP DOI BibTeX RDF	Power Estimation, Leakage Power, Linear Regression, Deep Submicron
2	Lipeng Cao	Circuit power estimation using pattern recognition techniques.	ICCAD	2002	DBLP DOI BibTeX RDF
2	Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner	Efficient estimation of signal transition activity in MAC architectures.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, MAC, power estimation, transition activity