Search results for "power model"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung	Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	IPI power model, black-box power model, prefetch power model, processor power modeling, software power estimation
3	Jaebok Park, Hyunwoo Joe, Hyungshin Kim	Automatic Power Model Generation for Sensor Network Simulator.	ICESS	2007	DBLP DOI BibTeX RDF	energy consumption estimation, sensor network, ubiquitous computing, embedded system, power model
3	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
2	Ruzica Jevtic, Carlos Carreras	Analytical High-Level Power Model for LUT-Based Components.	PATMOS	2008	DBLP DOI BibTeX RDF
2	Balaji V. Iyer, Thomas M. Conte	A Power Model for Register-Sharing Structures.	DIPES	2008	DBLP DOI BibTeX RDF
2	Ashish Mathur, Sourav Roy, Rajat Bhatia, Arup Chakraborty, Vijay Bhargava, Jatin Bhartia	JouleQuest: An Accurate Power Model for the StarCore DSP Platform.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Emmanuel M. Pothos, J. Gerard Wolff	The Simplicity and Power model for inductive inference.	Artif. Intell. Rev.	2006	DBLP DOI BibTeX RDF	Learning, Categorization, Cognitive science, Simplicity
2	Arrvindh Shriraman, Nagarajan Venkateswaran, Niranjan Soundararajan	PASCOM: Power Model for Supercomputers.	ARCS	2006	DBLP DOI BibTeX RDF
2	Sandro Penolazzi, Axel Jantsch	A High Level Power Model for the Nostrum NoC.	DSD	2006	DBLP DOI BibTeX RDF
2	Akhilesh Kumar, Mohab Anis	An analytical state dependent leakage power model for FPGAs.	DATE	2006	DBLP DOI BibTeX RDF
2	Kara K. W. Poon, Steven J. E. Wilton, Andy Yan	A detailed power model for field-programmable gate arrays.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Power estimation model, architecture, sensitivity analysis, power consumption
2	Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel	A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction.	PATMOS	2005	DBLP DOI BibTeX RDF
2	Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov	A retention-aware test power model for embedded SRAM.	ASP-DAC	2005	DBLP DOI BibTeX RDF	data retention fault test, multiple embedded SRAMs, test power modeling, test scheduling
2	Yan Lin, Fei Li, Lei He	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
2	Seongmoo Heo, Krste Asanovic	Replacing global wires with an on-chip network: a power analysis.	ISLPED	2005	DBLP DOI BibTeX RDF	on-chip network power model, tile size, wire power model, pipelining, router, tiled architecture
2	Hangsheng Wang, Li-Shiuan Peh, Sharad Malik	A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers.	IEEE Micro	2003	DBLP DOI BibTeX RDF
2	Pallav Gupta, Lin Zhong, Niraj K. Jha	A High-level Interconnect Power Model for Design Space Exploration.	ICCAD	2003	DBLP DOI BibTeX RDF
2	Fei Li, Deming Chen, Lei He, Jason Cong	Architecture evaluation for power-efficient FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA power model, low power design, FPGA architecture
2	Kara K. W. Poon, Andy Yan, Steven J. E. Wilton	A Flexible Power Model for FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
2	Hangsheng Wang, Li-Shiuan Peh, Sharad Malik	A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers.	Hot Interconnects	2002	DBLP DOI BibTeX RDF
2	Hyunsik Im	Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model).	ISLPED	2002	DBLP DOI BibTeX RDF	?-power model, MOSFET modeling, Saturation current
2	Susan Craw, Robin Boswell	Debugging knowledge-based applications with a generic toolkit.	ICTAI	2000	DBLP DOI BibTeX RDF	generic toolkit, knowledge refinement tools, knowledge based system maintenance, knowledge based system debugging, fault correction, KRUSTWorks toolkit, aerospace knowledge-based systems, knowledge based systems, knowledge engineering, program debugging, POWER-MODEL, CLIPS, aerospace computing, shells, fault identification
1	Christian Damgaard	Estimating plant allometric relationships in a power model with a minimum size of allocation.	Ecological Informatics	2012	DBLP DOI BibTeX RDF
1	Roberta Piscitelli, Andy D. Pimentel	A Signature-Based Power Model for MPSoC on FPGA.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Geir Olav Dyrkolbotn, Knut Wold, Einar Snekkenes	Layout Dependent Phenomena A New Side-channel Power Model.	JCP	2012	DBLP DOI BibTeX RDF
1	Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich	Variation-aware leakage power model extraction for system-level hierarchical power analysis.	DATE	2012	DBLP BibTeX RDF
1	Roberta Piscitelli, Andy D. Pimentel	A High-Level Power Model for MPSoC on FPGA.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Bing Guo, Yan Shen, Xiao Bin Liu, Qi Li, Ji He Wang, Yuan Sheng Wu	An Embedded Software Fusion Power Model Based on Algorithm and Micro-architectural Level.	CIS	2011	DBLP DOI BibTeX RDF
1	Jae Hoon Choi, Heung-Gyoon Ryu	Power Model and Analysis of Wireless Transceiver System.	FGIT-FGCN	2011	DBLP DOI BibTeX RDF
1	Massimo Alioto, Massimo Poli, Santina Rocchi	A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Thomas Maugey, Jérôme Gauthier, Béatrice Pesquet-Popescu, Christine Guillemot	Using an exponential power model forwyner ziv video coding.	ICASSP	2010	DBLP DOI BibTeX RDF
1	Jing Cao, Albert Nymeyer	High-fidelity markovian power model for protocols.	DATE	2010	DBLP BibTeX RDF
1	Vidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R. Stan	FlashPower: A detailed power model for NAND flash memory.	DATE	2010	DBLP BibTeX RDF
1	Lide Zhang, Birjodh Tiwana, Zhiyun Qian, Zhaoguang Wang, Robert P. Dick, Zhuoqing Morley Mao, Lei Yang	Accurate online power estimation and automatic battery behavior based power model generation for smartphones.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Xi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley Mao	Performance and power modeling in a multi-programmed multi-core environment.	DAC	2010	DBLP DOI BibTeX RDF	performance modeling, assignment, power modeling
1	Sunpyo Hong, Hyesoon Kim	An integrated GPU power and performance model.	ISCA	2010	DBLP DOI BibTeX RDF	GPU architecture, performance, energy, analytical model, CUDA, power estimation
1	Seung Eun Lee, Nader Bagherzadeh	A high level power model for Network-on-Chip (NoC) router.	Computers & Electrical Engineering	2009	DBLP DOI BibTeX RDF
1	Saktioto, Jalil Ali, Mohammed Fadhali	A Simplified Coupling Power Model of Single Mode Fiber Fusion at Coupling Length.	Asia International Conference on Modelling and Simulation	2009	DBLP DOI BibTeX RDF
1	Madhu Saravana Sibi Govindan, Stephen W. Keckler, Doug Burger	End-to-end validation of architectural power models.	ISLPED	2009	DBLP DOI BibTeX RDF	architectural power models, measurement, validation
1	Daniel Schmidt 0001, Norbert Wehn	DRAM power management and energy consumption: a critical assessment.	SBCCI	2009	DBLP DOI BibTeX RDF	modelling, measurement, power management, SDRAM
1	Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic	Floorplan-based FPGA interconnect power estimation in DSP circuits.	SLIP	2009	DBLP DOI BibTeX RDF	fpga, low power, interconnects, power estimation
1	Robert P. McEvoy, Colin C. Murphy, William P. Marnane, Michael Tunstall	Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs.	TRETS	2009	DBLP DOI BibTeX RDF	secure logic, FPGA, Side-channel attacks, DPA, Whirlpool
1	Meikang Qiu, Laurence Tianruo Yang, Edwin Hsing-Mean Sha	Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC.	CSE	2009	DBLP DOI BibTeX RDF
1	Oscar Chuy, Emmanuel G. Collins Jr., Wei Yu, Camilo Ordonez	Power modeling of a skid steered wheeled robotic ground vehicle.	ICRA	2009	DBLP DOI BibTeX RDF
1	Lei Liu, Guanhua Yan, Xinwen Zhang, Songqing Chen	VirusMeter: Preventing Your Cellphone from Spies.	RAID	2009	DBLP DOI BibTeX RDF	mobile malware, mobile device security, anomaly detection, power consumption
1	Hui Liu, Zili Shao, Meng Wang, Junzhao Du, Chun Jason Xue, Zhiping Jia	Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Periodic dependent tasks, Scheduling, Multimedia, Real-time, Dynamic voltage scaling (DVS), Multi-core, Software pipelining, Retiming
1	Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest	Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC)
1	Tal Rusak, Philip Alexander Levis	Investigating a physically-based signal power model for robust low power wireless link simulation.	MSWiM	2008	DBLP DOI BibTeX RDF	wireless link simulation, wireless sensor networks
1	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt	Methodology for multi-granularity embedded processor power model generation for an ESL design flow.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	system-on-chip, embedded processor, power modeling, esl
1	Richard Trihy	Addressing library creation challenges from recent Liberty extensions.	DAC	2008	DBLP DOI BibTeX RDF	Liberty, Liberty NCX, composite current source (CCS) models, nonlinear delay model (NLDM), nonlinear power model (NLPM), HSPICE
1	Lerong Cheng, Yan Lin, Lei He	Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA power model, FPGA architecture
1	Youngjin Cho, Younghyun Kim, Sangyoung Park, Naehyuck Chang	System-level power estimation using an on-chip bus performance monitoring unit.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Md. Rezaul Hoque Khan, Roberto Passerone, David Macii	FZepel: RF-level power consumption measurement (RF-PM) for Zigbee wireless sensor network-towards cross layer optimization.	ETFA	2008	DBLP DOI BibTeX RDF
1	Huiyun Li, Keke Wu, Bo Peng, Yiwei Zhang, Xinjian Zheng, Fengqi Yu	Enhanced Correlation Power Analysis Attack on Smart Card.	ICYCS	2008	DBLP DOI BibTeX RDF
1	S. Huang, Y. Luo, W. Feng	Modeling and analysis of power in multicore network processors.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang	Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF	interconnnection, reliability, low power, network-on-chip
1	Nazanin Rahnavard, Badri N. Vellambi, Faramarz Fekri	Distributed Protocols for Finding Low-Cost Broadcast and Multicast Trees in Wireless Networks.	SECON	2008	DBLP DOI BibTeX RDF
1	Yongchang Li, Michael Balchanos, Bassem Nairouz, Neil Weston, Dimitri Mavris	Modeling and simulation of integrated intelligent systems.	Winter Simulation Conference	2008	DBLP DOI BibTeX RDF
1	Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng	Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Shu Xiao, Edmund Ming-Kit Lai	A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors.	IEEE Transactions on Signal Processing	2008	DBLP DOI BibTeX RDF
1	Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo	Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu	An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	M. Abdelaziz Elaabid, Sylvain Guilley, Philippe Hoogvorst	Template Attacks with a Power Model.	IACR Cryptology ePrint Archive	2007	DBLP BibTeX RDF
1	Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau	Power model validation through thermal measurements.	ISCA	2007	DBLP DOI BibTeX RDF	power and thermal measurements
1	William Lloyd Bircher, Lizy K. John	Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events.	ISPASS	2007	DBLP DOI BibTeX RDF	power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model
1	Reza Moraveji, Hamid Sarbazi-Azad, Maghsoud Abbaspour	Optimal Placement of Frequently Accessed IPs in Mesh NoCs.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	Latency model, IPs/Cores mapping, System on chip, Network on chip, Mesh, Power model
1	Hushrav Mogal, Kia Bazargan	Microarchitecture floorplanning for sub-threshold leakage reduction.	DATE	2007	DBLP DOI BibTeX RDF
1	Stephan Hengstler, Daniel Prashanth, Sufen Fong, Hamid K. Aghajan	MeshEye: a hybrid-resolution smart camera mote for applications in distributed intelligent surveillance.	IPSN	2007	DBLP DOI BibTeX RDF	mote architecture, wireless sensor networks, power efficiency, smart cameras, distributed intelligence
1	Zhenghua Xue, Xiaoshe Dong, Siyuan Ma, Shengqun Fan, Yiduo Mei	An Energy-Efficient Management Mechanism for Large-Scale Server Clusters.	APSCC	2007	DBLP DOI BibTeX RDF
1	Peter van Stralen, Andy D. Pimentel	Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration.	ESTImedia	2007	DBLP DOI BibTeX RDF
1	Yoshiyuki Higashi, Kazuo Tanaka, Hiroshi Ohtake, Hua O. Wang	Construction of simulation model of a flying robot with variable attack angle mechanism.	IROS	2007	DBLP DOI BibTeX RDF
1	Prakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan	Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC Platform.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Meng Wang, Zili Shao, Chun Xue, Edwin Hsing-Mean Sha	Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors.	RTCSA	2007	DBLP DOI BibTeX RDF
1	Holger Blume, Jörg von Livonius, Lisa Rotenberg, Tobias G. Noll, Harald Bothe, Jörg Brakensiek	Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform.	ICSAMOS	2007	DBLP DOI BibTeX RDF
1	Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan	Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Giovanni Beltrame, Donatella Sciuto, Cristina Silvano	Multi-Accuracy Power and Performance Transaction-Level Modeling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena	Switching Activity Models for Power Estimation in FPGA Multipliers.	ARC	2007	DBLP DOI BibTeX RDF
1	Guochen Hua, Meng Wang, Zili Shao, Hui Liu, Chun Xue	Real-Time Loop Scheduling with Energy Optimization Via DVS and ABB for Multi-core Embedded System.	EUC	2007	DBLP DOI BibTeX RDF
1	Ani Nahapetian, Foad Dabiri, Miodrag Potkonjak, Majid Sarrafzadeh	Optimization for Real-Time Systems with Non-convex Power Versus Speed Models.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Je-Hoon Lee, Young-Sin Cho, Seok-Man Kim, Kyoung-Rok Cho	On-Chip Bus Modeling for Power and Performance Estimation.	SAMOS	2007	DBLP DOI BibTeX RDF	bus modeling, bus latency, SoC, on-chip bus
1	Ke Ning, David R. Kaeli	Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.	T. HiPEAC	2007	DBLP DOI BibTeX RDF	embedded systems, power-aware, external memory, media processor, bus arbitration
1	Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson	Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.	ISQED	2006	DBLP DOI BibTeX RDF
1	Jinwen Xi, Peixin Zhong	A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	network-on-chip, SystemC, energy model
1	Dakai Zhu, Hakan Aydin	Energy management for real-time embedded systems with reliability requirements.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti, Naehyuck Chang	An optimal analytical solution for processor speed control with thermal constraints.	ISLPED	2006	DBLP DOI BibTeX RDF	optimal control, temperature, DVFS, thermal management, DTM
1	Axel Reimer, Arne Schulz, Wolfgang Nebel	Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs.	ISLPED	2006	DBLP DOI BibTeX RDF	FPGA power estimation, RT-level power modeling, high-level power estimation
1	Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Compiler-directed thermal management for VLIW functional units.	LCTES	2006	DBLP DOI BibTeX RDF	VLIW, thermal, IPC
1	Yongpan Liu, Yu Wang 0002, Feng Zhang, Rong Luo, Hui Wang 0004	A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Qiang Xu, Baosheng Wang, F. Y. Young	Retention-Aware Test Scheduling for BISTed Embedded SRAMs.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton	Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays.	FPL	2006	DBLP DOI BibTeX RDF
1	Luca Negri, Davide Zanetti	Power/Performance Tradeoffs in Bluetooth Sensor Networks.	HICSS	2006	DBLP DOI BibTeX RDF
1	Hakan Aydin, Vinay Devadas, Dakai Zhu	System-Level Energy Management for Periodic Real-Time Tasks.	RTSS	2006	DBLP DOI BibTeX RDF
1	Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann	Memory performance prediction for high-performance microprocessors at deep submicrometer technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	RTL-Aware Cycle-Accurate Functional Power Estimation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Erik Larsson, Zebo Peng	Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	test set selection, TAM design, power consumption, hot-spots, Test scheduling, design exploration
1	Lin Zhong, Niraj K. Jha	Dynamic Power Optimization Targeting User Delays in Interactive Systems.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	human-computer interaction, user interfaces, Energy efficiency, power management
1	Zhimin Chen, Yujie Zhou	Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage.	CHES	2006	DBLP DOI BibTeX RDF	Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
1	Tzong-Yen Lin, Rong-Guey Chang	Power-Aware Instruction Scheduling.	EUC	2006	DBLP DOI BibTeX RDF
1	Hui Wu, Sridevan Parameswaran	Minimising the Energy Consumption of Real-Time Tasks with Precedence Constraints on a Single Processor.	EUC	2006	DBLP DOI BibTeX RDF
1	Luca Negri, Lothar Thiele	Power Management for Bluetooth Sensor Networks.	EWSN	2006	DBLP DOI BibTeX RDF