Search results for "power optimization"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Philippe Grosse, Yves Durand, Paul Feautrier	Methods for power optimization in SOC-based data flow systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	4G base-band modem, data-driven SOC, synchronous data-flow graph, Power optimization
3	Xuexia Zhang, Weirong Chen	Multi-objective Oriented Search Algorithm for Multi-objective Reactive Power Optimization.	ICIC	2009	DBLP DOI BibTeX RDF	MOOSA, multi-objective reactive power optimization, Pareto front, Pareto-optimal solutions
3	Bu-han Zhang, Kai Wang, Chao Yang, Yan Li, Chengxiong Mao, Xin-bo Ruan, Yong-feng Yao, Hong-xian Hu	Two-Phase Dynamic Reactive Power Optimization Based on Improved Genetic Algorithm.	ISNN	2009	DBLP DOI BibTeX RDF	Dynamic reactive power optimization, Two-phase, Improved genetic algorithm, Regulation times, Parallel computing, Dynamic programming
3	Bing Guo, Dianhui Wang, Yan Shen, Zhishu Li	A Hopfield neural network approach for power optimization of real-time operating systems.	Neural Computing and Applications	2008	DBLP DOI BibTeX RDF	SoC, Power optimization, RTOS, Hopfield neural network, Hardware-software partitioning
3	Xuejun Yang, Huizhan Yi, Xiangli Qu, Haifang Zhou	Compiler-directed power optimization of high-performance interconnection networks for load-balancing MPI applications.	Frontiers of Computer Science in China	2007	DBLP DOI BibTeX RDF	compiler-directed power optimization, high performance interconnection network, MPI application
3	Jorgen Peddersen, Sri Parameswaran	CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time.	ASP-DAC	2007	DBLP DOI BibTeX RDF	dynamic power optimization, CLIPPER, counter-based low impact processor, run-time power optimization, power consumption, energy consumption
3	Inki Hong, Miodrag Potkonjak	Power optimization in disk-based real-time application specific systems.	ICCAD	1996	DBLP DOI BibTeX RDF	design process abstractions, disk data assignment, electronic components, magnetic disks, mechanical-electronic subsystems, power consumption model, real-time application specific systems, task scheduling, power optimization, power reduction, power minimization, magnetic disc storage, disk drives
2	Hamid Shojaei, Tai-Hsuan Wu, Azadeh Davoodi, Twan Basten	A pareto-algebraic framework for signal power optimization in global routing.	ISLPED	2010	DBLP DOI BibTeX RDF	pareto algebra, global routing, dynamic power
2	Guiping Xiao, Jiansheng Mei	Reactive Power Optimization Based on Hybrid Particle Swarm Optimization Algorithm.	APWCS	2010	DBLP DOI BibTeX RDF	reactive power optimization, differential evolution, power system, Hybrid particle swarm optimization
2	Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong	Incremental power optimization for multiple supply voltage design.	ISQED	2009	DBLP DOI BibTeX RDF
2	Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao	Clock gating effectiveness metrics: Applications to power optimization.	ISQED	2009	DBLP DOI BibTeX RDF
2	Wen-hua Zhou, Zhen-jie Jiang	Hybrid Cataclysmic Genetic Algorithm Used to Reactive Power Optimization.	NCM	2009	DBLP DOI BibTeX RDF	Cataclysmic generic algorithm, Reactive power optimization, Fuzzy control
2	Tang Lung Cheung, Kari Okamoto, Frank Maker III, Xin Liu, Venkatesh Akella	Markov decision process (MDP) framework for optimizing software on mobile phones.	EMSOFT	2009	DBLP DOI BibTeX RDF	talk time extension, user-profile driven, mobile phones, markov-decision process, power optimization, android
2	Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh	General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker	Towards Novel Approaches in Design Automation for FPGA Power Optimization.	PATMOS	2008	DBLP DOI BibTeX RDF
2	Pablo Aguirre, Fernando Silveira	CMOS op-amp power optimization in all regions of inversion using geometric programming.	SBCCI	2008	DBLP DOI BibTeX RDF	optimization, CMOS, analog, geometric programming, automatic design
2	Tao Luo, David Newmark, David Z. Pan	Total power optimization combining placement, sizing and multi-Vt through slack distribution management.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Hassan Ghasemzadeh, Eric Guenterberg, Katherine Gilani, Roozbeh Jafari	Action coverage formulation for power optimization in body sensor networks.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Tinghong Zhao, Zhijun Wang, Zibin Man	A CGS-MSM PGA Based on Multi-agent and Its Application in Reactive Power Optimization.	CSSE	2008	DBLP DOI BibTeX RDF
2	Yue Chi, Zhushi Xie, Kewen Xia, Xin Liu	Static Power Optimization for CMOS Combinational Circuit Based on Bacterial Colony Chemotaxis Algorithm.	CSSE	2008	DBLP DOI BibTeX RDF
2	Zhongxu Li, Yutian Liu, Rushui Liu, Xinsheng Niu	Network Partition for Distributed Reactive Power Optimization in Power Systems.	ICNSC	2008	DBLP DOI BibTeX RDF
2	Jin Ouyang, Yuan Xie	Power optimization for FinFET-based circuits using genetic algorithms.	SoCC	2008	DBLP DOI BibTeX RDF
2	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
2	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Timing-aware power-optimal ordering of signals.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Wire ordering, wire spacing, power optimization, interconnect optimization
2	Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong	Interconnect Power Optimization Based on Timing Analysis.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh	Soft Error-Aware Power Optimization Using Gate Sizing.	PATMOS	2007	DBLP DOI BibTeX RDF
2	Parth Malani, Prakash Mukre, Qinru Qiu	Power optimization for conditional task graphs in DVS enabled multiprocessor systems.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
2	Hung-Yi Liu, Wan-Ping Lee, Yao-Wen Chang	A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages.	DAC	2007	DBLP DOI BibTeX RDF
2	Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal, Alexander Pratsch, Eike Schmidt	System level clock tree synthesis for power optimization.	DATE	2007	DBLP DOI BibTeX RDF
2	Fei Gong, Xiaobo Wu	Interactive presentation: System level power optimization of Sigma-Delta modulator.	DATE	2007	DBLP DOI BibTeX RDF
2	Valentina Salapura, Robert Walkup, Alan Gara	Exploiting Workload Parallelism for Performance and Power Optimization in Blue Gene.	IEEE Micro	2006	DBLP DOI BibTeX RDF	application studies resulting in better multiple-processor systems, super (very large) computers, Blue Gene/L system, architecture, parallelism, parallelism, interprocessor communications, processor architectures, power optimization, computer systems organization, computer system implementation
2	Arnab Chakrabarti, Ashutosh Sabharwal, Behnaam Aazhang	Communication power optimization in a sensor network with a path-constrained mobile observer.	TOSN	2006	DBLP DOI BibTeX RDF	Sensor network, communication, mobility, power, queuing
2	Lin Zhong, Niraj K. Jha	Dynamic Power Optimization Targeting User Delays in Interactive Systems.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	human-computer interaction, user interfaces, Energy efficiency, power management
2	Ke-yan Liu, Wanxing Sheng, Yun-hua Li	Research on Reactive Power Optimization Based on Immunity Genetic Algorithm.	ICIC	2006	DBLP DOI BibTeX RDF
2	B. Chung, J. B. Kuo	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Amin Shameli, Payam Heydari	A novel power optimization technique for ultra-low power RFICs.	ISLPED	2006	DBLP DOI BibTeX RDF	radio-frequency integrated circuit, CMOS, ultra-low power, low-noise amplifier
2	Fei Hu, Vishwani D. Agrawal	Input-specific dynamic power optimization for VLSI circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	dynamic power optimization, glitch reduction, input specific
2	Razvan Racu, Arne Hamann, Rolf Ernst, Bren Mochocki, Xiaobo Sharon Hu	Methods for power optimization in distributed embedded systems with real-time requirements.	CASES	2006	DBLP DOI BibTeX RDF	SymTA/S, real-time systems, evolutionary algorithms, dynamic voltage scaling, sensitivity analysis, timing analysis, power optimization
2	Jianxue Wang, Weichao Wang, Xifan Wang, Haoyong Chen, Xiuli Wang	Cooperative Co-evolutionary Approach Applied in Reactive Power Optimization of Power System.	ICNC	2006	DBLP DOI BibTeX RDF
2	Radu Cornea, Alexandru Nicolau, Nikil D. Dutt	Software annotations for power optimization on mobile devices.	DATE	2006	DBLP DOI BibTeX RDF
2	B. Chung, J. B. Kuo	Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Bing Guo, Dianhui Wang, Yan Shen, Zhishu Li	Neurocomputing for Minimizing Energy Consumption of Real-Time Operating System in the System-on-a-Chip.	ICONIP	2006	DBLP DOI BibTeX RDF	SoC, Power optimization, RTOS, Hopfield neural network, Hardware-software partitioning
2	Gaurav Bhaya, B. S. Manoj, C. Siva Ram Murthy	On the Power Optimization and Throughput Performance of Multihop Wireless Network Architectures.	HiPC	2005	DBLP DOI BibTeX RDF
2	Venkataraman Mahalingam, N. Ranganathan	A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection.	ISVLSI	2005	DBLP DOI BibTeX RDF
2	Leonardo Barboni, Rafaella Fiorelli	Design and power optimization of CMOS RF blocks operating in the moderate inversion region.	SBCCI	2005	DBLP DOI BibTeX RDF	amplifier design, radio frequency integrated circuits, CMOS integrated circuits, power optimization
2	Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee	Leakage power optimization with dual-Vth library in high-level synthesis.	DAC	2005	DBLP DOI BibTeX RDF	dual-Vth, optimization, high-level synthesis, leakage power
2	Jiachuan Shi, Yutian Liu	Fuzzy Evaluation Based Multi-objective Reactive Power Optimization in Distribution Networks.	FSKD	2005	DBLP DOI BibTeX RDF
2	Bo Yang, Ramesh Karri	Power optimization for universal hash function data path using divide-and-concatenate technique.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	divide-and-concatenate, power optimization, universal hash function
2	Il-Min Kim	Space-time power optimization of variable-rate space-time block codes based on successive interference cancellation.	IEEE Transactions on Communications	2004	DBLP DOI BibTeX RDF
2	Ashok K. Murugavel, N. Ranganathan	Gate Sizing and Buffer Insertion using Economic Models for Power Optimization.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Krishnan Srinivasan, Karam S. Chatha	An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Lin Zhong, Niraj K. Jha	Dynamic Power Optimization of Interactive Systems.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Keoncheol Shin, Taewhan Kim	Leakage power minimization for the synthesis of parallel multiplier circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	synthesis, power optimization
2	R. Reed Taylor, Herman Schmit	Creating a power-aware structured ASIC.	ISLPED	2004	DBLP DOI BibTeX RDF	VPGA, low-power, voltage scaling, power optimization, gate sizing, structured ASIC
2	Shivajit Mohapatra, Nalini Venkatasubramanian	A Game Theoretic Approach for Power Aware Middleware.	Middleware	2004	DBLP DOI BibTeX RDF	power-aware middleware, game theory, power optimization
2	Kyu-won Choi, Abhijit Chatterjee	UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI.	ISLPED	2003	DBLP DOI BibTeX RDF	device and interconnect co-optimization, nanometer design, time slack distribution, low-power design
2	Li-Chuan Weng, Xiaojun Wang, Bin Liu 0001	A Survey of Dynamic Power Optimization Techniques.	IWSOC	2003	DBLP DOI BibTeX RDF
2	Li Shang, Li-Shiuan Peh, Niraj K. Jha	Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks.	HPCA	2003	DBLP DOI BibTeX RDF
2	Qi Wang, Sumit Roy	RTL Power Optimization with Gate-Level Accuracy.	ICCAD	2003	DBLP DOI BibTeX RDF
2	N. Ranganathan, Ashok K. Murugavel	A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization.	ICCD	2003	DBLP DOI BibTeX RDF
2	Xuning Chen, Li-Shiuan Peh	Leakage power modeling and optimization in interconnection networks.	ISLPED	2003	DBLP DOI BibTeX RDF	interconnection networks, leakage power, power optimization
2	Nathalie Julien, S. Gailhard, Eric Martin	Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	dedicated architecture, data format, real time system, low power, high level synthesis, design methodology, discrete wavelet transform, power optimization
2	Asim Smailagic, Matthew Ettus	System Design and Power Optimization for Mobile Computers.	ISVLSI	2002	DBLP DOI BibTeX RDF
2	Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min	Test Power Optimization Techniques for CMOS Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
2	Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh	On gate level power optimization using dual-supply voltages.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi	Partial bus-invert coding for power optimization of application-specific systems.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Inki Hong, Miodrag Potkonjak, Ramesh Karri	Power optimization using divide-and-conquer techniques for minimization of the number of operations.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	code generation, transformations
2	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register transfer level power optimization with emphasis on glitch analysis and reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
2	Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer	Power optimization of core-based systems by address bus encoding.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
2	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru	A power optimization method considering glitch reduction by gate sizing.	ISLPED	1998	DBLP DOI BibTeX RDF
2	S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization. (PDF / PS)	ICTAI	1997	DBLP DOI BibTeX RDF
2	Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru	Timing and Power Optimization by Gate Sizing Considering False Paths.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
1	Ioannis Krikidis, Themistoklis Charalambous, John S. Thompson	Stability Analysis and Power Optimization for Energy Harvesting Cooperative Networks.	IEEE Signal Process. Lett.	2012	DBLP DOI BibTeX RDF
1	José Manuel Velasco, David Atienza, Katzalin Olcoz	Memory power optimization of Java-based embedded systems exploiting garbage collection information.	Journal of Systems Architecture - Embedded Systems Design	2012	DBLP DOI BibTeX RDF
1	Aris L. Moustakas, Nicholas Bambos	Power Optimization on a Network: The effects of randomness	CoRR	2012	DBLP BibTeX RDF
1	Kan Wang, Sheqin Dong, Satoshi Goto	Voltage island-driven power optimization for application specific network-on-chip design.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Shao-Yi Chien, Teng-Yuan Cheng, Chieh-Chuan Chiu, Pei-Kuei Tsung, Chia-han Lee, V. Srinivasa Somayazulu, Yen-Kuang Chen	Power optimization of wireless video sensor nodes in M2M networks.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin	Crosstalk-aware power optimization with multi-bit flip-flops.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Xiaodong Wang, Yanjun Yao, Xiaorui Wang, Kefa Lu, Qing Cao	CARPO: Correlation-aware power optimization in data center networks.	INFOCOM	2012	DBLP DOI BibTeX RDF
1	Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh	On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Guowang Miao, Nageen Himayat, Geoffrey Ye Li, Shilpa Talwar	Distributed Interference-Aware Energy-Efficient Power Optimization.	IEEE Transactions on Wireless Communications	2011	DBLP DOI BibTeX RDF
1	Rahul Nagpal, Y. N. Srikant	Compiler-assisted power optimization for clustered VLIW architectures.	Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Wei Jiang, Bin Liu 0006, Yi Zou	Automatic memory partitioning and scheduling for throughput and power optimization.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Fuyu Chen, Weifeng Su, Stella N. Batalama, John D. Matyjas	Joint Power Optimization for Multi-Source Multi-Destination Relay Networks.	IEEE Transactions on Signal Processing	2011	DBLP DOI BibTeX RDF
1	Mark Po-Hung Lin, Chih-Cheng Hsu, Yao-Tsung Chang	Post-Placement Power Optimization With Multi-Bit Flip-Flops.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Huan Ren, Shantanu Dutt	Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous Vdd, Vth Assignments, Gate Sizing, and Placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Farzad Parvaresh, Raúl H. Etkin	Efficient Capacity Computation and Power Optimization for Relay Networks	CoRR	2011	DBLP BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Jintae Kim, S. Limotyrakis, Chih-Kong Ken Yang	Multilevel Power Optimization of Pipelined A/D Converters.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Lijun Li, Michael M. Green	Power Optimization of an 11.75-Gb/s Combined Decision Feedback Equalizer and Clock Data Recovery Circuit in 0.18- μħbox m CMOS.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Chao Wang, Gang Yao, Xin Wang, Yihui Zheng, Lidan Zhou, Qingshan Xu, Xinyuan Liang	Reactive Power Optimization Based on Particle Swarm Optimization Algorithm in 10kV Distribution Network.	ICSI	2011	DBLP DOI BibTeX RDF
1	Rohit Agrawal, C. Sasi Kumar, Darshan Moodgal	Power Optimization Techniques for Segmented Digital Displays.	ACC	2011	DBLP DOI BibTeX RDF
1	A. S. Radhamani, E. Baburaj	Research on Power Optimization Techniques for Multi Core Architectures.	ACC	2011	DBLP DOI BibTeX RDF
1	G. Indumathi, K. V. Ramakrishnan	Study and Analysis of Power Optimization Techniques for Embedded Systems.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Manuj R. Sabharwal	Software power optimization: analysis and optimization for energy-efficient software.	ISLPED	2011	DBLP BibTeX RDF
1	Antonio Artés, José Luis Ayala, Ashoka Visweswara Sathanur, Jos Huisken, Francky Catthoor	Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
1	Tanu Preet Singh, Manmeet Kaur, Vishal Sharma	Dead State Recovery Based Power Optimization Routing Protocol for MANETs (DSPO).	HPAGC	2011	DBLP DOI BibTeX RDF
1	Hasan Kartlak, Niyazi Odabasioglu, Aydin Akan	Joint multiple relay selection and power optimization in two-way relay networks.	ICUMT	2011	DBLP BibTeX RDF
1	Patricio Torres, Jan-Willem van Wingerden, Michel Verhaegen	Modeling of the flow in wind farms for total power optimization.	ICCA	2011	DBLP DOI BibTeX RDF
1	Omid Palizban, Saad Mekhilef	Power optimization and static performance investigation of an island-mode doubly-fed induction generator (DFIG).	ICCSCE	2011	DBLP DOI BibTeX RDF