Search results for "power-delay optimization"

Searching for phrase power-delay optimization (changed automatically) with no syntactic query expansion in all metadata.

Found 7 publication records. Showing 7 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	The complexity of VLSI power-delay optimization by interconnect resizing.	J. Comb. Optim.	2012	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Interconnect power and delay optimization by dynamic programming in gridded design rules.	ISPD	2010	DBLP DOI BibTeX RDF	gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Power-delay optimization in VLSI microprocessors by wire spacing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Wire spacing, power optimization, interconnect optimization, delay-optimization
1	Massimo Alioto, Gaetano Palumbo	Power-delay optimization in MCML tapered buffers.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs.	ISQED	2008	DBLP DOI BibTeX RDF
1	Tohru Ishihara, Hiroto Yasuura	Voltage scheduling problem for dynamically variable voltage processors.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Ram K. Krishnamurthy, L. Richard Carley	Exploring the design space of mixed swing quadrail for low-power digital circuits.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF

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