Search results for "process scaling"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Kenneth B. Kent, Jonathan Rose	VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling.	TRETS	2011	DBLP DOI BibTeX RDF
1	Edward A. Stott, Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Degradation in FPGAs: measurement and modelling.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, self test
1	Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Jonathan Rose	VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, architecture, cad
1	Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas	The BubbleWrap many-core: popping cores for sequential acceleration.	MICRO	2009	DBLP DOI BibTeX RDF	power wall, process scaling, processor aging, voltage scaling
1	David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester	Vicis: a reliable network for unreliable silicon.	DAC	2009	DBLP DOI BibTeX RDF	hard faults, fault tolerance, built-in-self-test, Network-on-Chip, reconfiguration, torus, N-modular redundancy
1	Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger	Architecting phase change memory as a scalable dram alternative.	ISCA	2009	DBLP DOI BibTeX RDF	dram alternative, performance, scalability, power, energy, phase change memory, pcm, endurance
1	Krisztián Flautner	Life on the Treadmill.	ARCS	2009	DBLP DOI BibTeX RDF
1	David R. Bild, Sanchit Misra, Thidapat Chantem, Prabhat Kumar, Robert P. Dick, Xiaobo Sharon Hu, Li Shang, Alok N. Choudhary	Temperature-aware test scheduling for multiprocessor systems-on-chip.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Krisztián Flautner	The Wall Ahead is Made of Rubber.	DDECS	2008	DBLP DOI BibTeX RDF
1	Elena Dubrova	Self-Organization for Fault-Tolerance.	IWSOS	2008	DBLP DOI BibTeX RDF
1	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	LEAF: A System Level Leakage-Aware Floorplanner for SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs
1	Federico Baronti, Roberto Roncella, Roberto Saletti, Paolo D'Abramo, L. Di Piro, H. Fabian, M. Giardi	The importance of At-Speed Scan Testing: an industrial experience.	DSD	2007	DBLP DOI BibTeX RDF
1	Krisztián Flautner	Blurring the Layers of Abstractions: Time to Take a Step Back?	IOLTS	2007	DBLP DOI BibTeX RDF
1	Mini Nanua, David Blaauw	Crosstalk Waveform Modeling Using Wave Fitting.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Krisztián Flautner	Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	typical-case operation, embedded systems, low power, signal processing
1	Robert C. Aitken	Reliability Issues for Embedded SRAM at 90nm and Below.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Dongwoo Lee, David Blaauw, Dennis Sylvester	Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif	An efficient surface-based low-power buffer insertion algorithm.	ISPD	2005	DBLP DOI BibTeX RDF	low-power design, buffer insertion, physical synthesis
1	Lei Wang	Error-tolerance memory Microarchitecture via Dynamic Multithreading.	ICCD	2005	DBLP DOI BibTeX RDF
1	Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang 0010	Performance Driven OPC for Mask Cost Reduction.	ISQED	2005	DBLP DOI BibTeX RDF
1	Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester	Selective gate-length biasing for cost-effective runtime leakage control.	DAC	2004	DBLP DOI BibTeX RDF	power, layout, manufacturability, leakage, OPC, lithography
1	Ketan N. Patel, Igor L. Markov	Error-correction and crosstalk avoidance in DSM busses.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	James Lin	Design technology challenges for system and chip level designs in very deep submicron technologies.	CODES+ISSS	2003	DBLP DOI BibTeX RDF
1	Ketan N. Patel, Igor L. Markov	Error-correction and crosstalk avoidance in DSM busses.	SLIP	2003	DBLP DOI BibTeX RDF	DSM busses, error-correction, crosstalk noise, bus encoding
1	M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John Poulton	CMOS High-Speed I/Os - Present and Future.	ICCD	2003	DBLP DOI BibTeX RDF
1	Pasquale Cocchini	A methodology for optimal repeater insertion in pipelined interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Pasquale Cocchini	Concurrent flip-flop and repeater insertion for high performance integrated circuits.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Spencer M. Gold, Richard B. Brown, Bruce Bernhardt	A Quantitative Approach to Nonlinear Process Design Rule Scaling.	ARVLSI	1999	DBLP DOI BibTeX RDF
1	Kenneth E. Hoganson	Workload Execution Strategies and Parallel Speedup on Clustered Computers.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	clustering, Parallel processing, efficiency, scaling, speedup