Search results for "process tolerant"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy	Process Variations and Process-Tolerant Design.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy	A process-tolerant cache architecture for improved yield in nanoscale technologies.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne Burleson	A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Ik Joon Chang, Sang Phill Park, Kaushik Roy	Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Myeong-Eun Hwang, Kaushik Roy	ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira	Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits.	DDECS	2008	DBLP DOI BibTeX RDF
1	Shreyas Sen, Vishwanath Natarajan, Rajarajan Senguttuvan, Abhijit Chatterjee	Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems.	DAC	2008	DBLP DOI BibTeX RDF	low power RF transceivers, process tolerant adaptive RF
1	Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.	JETC	2008	DBLP DOI BibTeX RDF	Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration
1	Myeong-Eun Hwang, Tamer Cakici, Kaushik Roy	Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling.	DATE	2007	DBLP DOI BibTeX RDF
1	Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy	Low-power process-variation tolerant arithmetic units using input-based elastic clocking.	ISLPED	2007	DBLP DOI BibTeX RDF	elastic clocking, process tolerant, low power
1	Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh	SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Quentin Diduck, John Liobe, Sadeka Ali, Martin Margala	Process tolerant calibration circuit for PLL applications with BIST.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Shubha Bommalingaiahnapallya, Ramesh Harjani	Process tolerant design of N-tone Sigma-Delta converters.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy	A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.	IOLTS	2005	DBLP DOI BibTeX RDF	Speed binning, delay measurement hardware, process variation
1	Vishak Venkatraman, Wayne Burleson	Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations.	ISQED	2005	DBLP DOI BibTeX RDF
1	Ron Wilson, Siva Narendra, Vivek De	Evening Panel Discussion: Process Variation: Is It Too Much to Handle? (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
1	Bapiraju Vinnakota, Wanli Jiang, Dechang Sun	Process-tolerant test with energy consumption ratio.	ITC	1998	DBLP DOI BibTeX RDF