Search results for "process variation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Amlan Ghosh, Rahul M. Rao, Richard B. Brown	A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation.	ISLPED	2009	DBLP DOI BibTeX RDF	fine-grain body-biasing, process variation compensation, slewrate
3	Aarti Choudhary, Sandip Kundu	A process variation tolerant self-compensating FinFET based sense amplifier design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	sense amplifier, robustness, process -variation, yield, sram, finfet
3	Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph	Process variation characterization of chip-level multiprocessors.	DAC	2009	DBLP DOI BibTeX RDF	software, process variation, characterization
3	Lang Lin, Wayne P. Burleson	Analysis and mitigation of process variation impacts on Power-Attack Tolerance.	DAC	2009	DBLP DOI BibTeX RDF	process variation, differential power analysis, Monte Carlo simulation, transistor sizing
3	Abhranil Maiti, Patrick Schaumont	Impact and compensation of correlated process variation on ring oscillator based puf.	FPGA	2009	DBLP DOI BibTeX RDF	correlated process variation, physical unclonable function (puf), ring oscillator (ro), fpga
3	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
3	Michael Leuchtenburg, Pritish Narayanan, Teng Wang, Csaba Andras Moritz	Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors.	NanoNet	2008	DBLP DOI BibTeX RDF	nanoscale processor, process variation, defect tolerance
3	Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas	ReCycle: : pipeline adaptation to tolerate process variation.	ISCA	2007	DBLP DOI BibTeX RDF	pipeline, process variation, clock skew
3	Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang	Principle hessian direction based parameter reduction for interconnect networks with process variation.	SLIP	2007	DBLP DOI BibTeX RDF	principle Hessian directions, process variation, timing analysis
3	Yan Lin, Lei He	Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, uncertainty, process variation, stochastic, physical synthesis
3	Mehrdad Nourani, Arun Radhakrishnan	Testing On-Die Process Variation in Nanometer VLSI.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	nanometer VLSI, ultra deep-submicron, fast Fourier transform, process variation, frequency domain, ring oscillator
3	Peng Yu, Sean X. Shi, David Z. Pan	Process variation aware OPC with variational lithography modeling.	DAC	2006	DBLP DOI BibTeX RDF	lithography modeling, process variation, OPC
3	Nandakumar P. Venugopal, Nihal Shastry, Shambhu J. Upadhyaya	Effect of Process Variation on the Performance of Phase Frequency Detector.	DFT	2006	DBLP DOI BibTeX RDF	Phase Frequency Detector (PFD), NFET, PFET, process variation, Monte Carlo simulation, Jitter, Phase noise
3	Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	Path delay test compaction with process variation tolerance.	DAC	2005	DBLP DOI BibTeX RDF	process variation, delay testing, path delay fault, test compaction
3	Louis Scheffer	Explicit computation of performance as a function of process variation.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	static timing, process variation, yield, statistical timing
3	Byungwoo Choi, D. M. H. Walker	Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation.	VTS	2000	DBLP DOI BibTeX RDF	interconnect coupling, delay fault model, process variation, timing analysis, delay fault test
2	Lin Huang, Qiang Xu	Performance yield-driven task allocation and scheduling for MPSoCs under process variation.	DAC	2010	DBLP DOI BibTeX RDF	performance yield, process variation, task scheduling
2	Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan	SRAM-based NBTI/PBTI sensor system design.	DAC	2010	DBLP DOI BibTeX RDF	PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI
2	Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi	Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks.	ISQED	2009	DBLP DOI BibTeX RDF
2	Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma	A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	current mode singnaling, dynamic overdriving, process variation tolerant
2	Kelageri Nagaraj, Sandip Kundu	Process variation mitigation via post silicon clock tuning.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	post-silicon tuning, performance, process variation
2	Spandana Remarsu, Sandip Kundu	On process variation tolerant low cost thermal sensor design in 32nm CMOS technology.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	self compensating comparator, dithering, thermal sensor
2	Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy	A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors.	DAC	2009	DBLP DOI BibTeX RDF	low power SRAM, supply voltage over-scaling, graceful degradation
2	Fang Gong, Hao Yu, Lei He	PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation.	DAC	2009	DBLP DOI BibTeX RDF	incremental precondition, parallel fast-multipole method, stochastic geometrical moments, capacitance extraction
2	Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng	Statistical reliability analysis under process variation and aging effects.	DAC	2009	DBLP DOI BibTeX RDF	process variations, yield, NBTI
2	Xin Fu, Tao Li, José A. B. Fortes	Soft error vulnerability aware process variation mitigation.	HPCA	2009	DBLP DOI BibTeX RDF
2	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design
2	Jifeng Chen, Jin Sun, Janet Meiling Wang	Robust interconnect communication capacity algorithm by geometric programming.	ISPD	2009	DBLP DOI BibTeX RDF	communication capacity, optimization, robust, uncertainty, process variation, geometric programming, ellipsoid
2	Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	ZerehCache: armoring cache architectures in high defect density technologies.	MICRO	2009	DBLP DOI BibTeX RDF	fault-tolerant cache, process variation, manufacturing yield
2	Wangyuan Zhang, Tao Li	Characterizing and mitigating the impact of process variations on phase change based memory systems.	MICRO	2009	DBLP DOI BibTeX RDF	process variation, memory system, phase change memory
2	Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002	Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.	MICRO	2009	DBLP DOI BibTeX RDF	3D die stacking, NUCA, process variation, DRAM
2	Siddharth Garg, Diana Marculescu	System-level throughput analysis for process variation aware multiple voltage-frequency island designs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	manufacturing process variations, maximum cycle mean, voltage-frequency islands, performance analysis, system-level design, Globally asynchronous locally synchronous
2	Guo Yu, Wei Dong, Zhuo Feng, Peng Li	Statistical Static Timing Analysis Considering Process Variation Model Uncertainty.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Yan Lin, Lei He, Mike Hutton	Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Shambhu J. Upadhyaya, Nandakumar P. Venugopal, Nihal Shastry, Srinivasan Gopalakrishnan, Bharath V. Kuppuswamy, Rana Bhowmick, Prerna Mayor	Design Considerations for High Performance RF Cores Based on Process Variation Study.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Cascode LNA, Corner analysis, Differential CMOS LNA, Phase frequency detector (PFD), Reuse topology, Process variation, Jitter, Phase noise, Noise figure, S-parameters, Monte Carlo analysis
2	Rasit Onur Topaloglu	Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics.	ISQED	2008	DBLP DOI BibTeX RDF	foldable electronics, nanoparticle interconnects, process variations
2	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
2	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design.	ISQED	2008	DBLP DOI BibTeX RDF
2	Jui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, Charlie Chung-Ping Chen	Process-Variation Statistical Modeling for VLSI Timing Analysis.	ISQED	2008	DBLP DOI BibTeX RDF	non-Gaussian model, VLSI, Process Variation, SSTA
2	Justin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole	Combating process variation on FPGAS with a precise at-speed delay measurement method.	FPL	2008	DBLP DOI BibTeX RDF
2	Mahmoud Ben Naser, Csaba Andras Moritz	Power and performance tradeoffs with process variation resilient adaptive cache architectures.	SBCCI	2008	DBLP DOI BibTeX RDF	process variations, leakage power, adaptive cache
2	Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin	Analysis and solutions to issue queue process variation.	DSN	2008	DBLP DOI BibTeX RDF
2	Xin Fu, Tao Li, José A. B. Fortes	NBTI tolerant microarchitecture design in the presence of process variation.	MICRO	2008	DBLP DOI BibTeX RDF
2	Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy	Process variation tolerant SRAM array for ultra low voltage applications.	DAC	2008	DBLP DOI BibTeX RDF	Schmitt trigger SRAM, low voltage/sub-threshold SRAM, process tolerance
2	Saihua Lin, Yu Wang 0002, Rong Luo, Huazhong Yang	A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Lerong Cheng, Yan Lin, Lei He	Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA power model, FPGA architecture
2	Yuanlin Lu, Vishwani D. Agrawal	Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen	Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Raghavendra K, Madhu Mutyam	Process Variation Aware Issue Queue Design.	DATE	2008	DBLP DOI BibTeX RDF
2	Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii	Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.	DATE	2008	DBLP DOI BibTeX RDF
2	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan	A nano-CMOS process variation induced read failure tolerant SRAM cell.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Shreyas Sen, Abhijit Chatterjee	Design of process variation tolerant radio frequency low noise amplifier.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
2	Love Singhal, Elaheh Bozorgzadeh	Process variation aware system-level task allocation using stochastic ordering of delay distributions.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Love Singhal, Sejong Oh, Eli Bozorgzadeh	Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	configuration selection, delay budgeting, process variation, task allocation, within-die variation, timing yield
2	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
2	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation Aware Spline Center and Range Modeling for Analog Circuit Performance.	ISQED	2008	DBLP DOI BibTeX RDF	Center and Range, Process Variation, Analog, Spline
2	Ashish Srivastava, T. Kachru, Dennis Sylvester	Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Shubhankar Basu, Ranga Vemuri	Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy	A process variation aware low power synthesis methodology for fixed-point FIR filters.	ISLPED	2007	DBLP DOI BibTeX RDF	fixed-point FIR filters, variation aware, low-power, synthesis
2	Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy	Low-power process-variation tolerant arithmetic units using input-based elastic clocking.	ISLPED	2007	DBLP DOI BibTeX RDF	elastic clocking, process tolerant, low power
2	Brandon L. Dell, Jonathan F. Bolus, Travis N. Blalock	An automated unique tagging system using CMOS process variation.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	AUTS, RFID, process variation
2	Kanak Agarwal, Sani R. Nassif	Characterizing Process Variation in Nanometer CMOS.	DAC	2007	DBLP DOI BibTeX RDF
2	Yuanlin Lu, Vishwani D. Agrawal	Statistical Leakage and Timing Optimization for Submicron Process Variation.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Madhu Mutyam, Narayanan Vijaykrishnan	Working with process variation aware caches.	DATE	2007	DBLP DOI BibTeX RDF
2	Nilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy	Process variation tolerant low power DCT architecture.	DATE	2007	DBLP DOI BibTeX RDF
2	Chao Yang, Andrew Mason	Precise RSSI with High Process Variation Tolerance.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Martin Hansson, Atila Alvandpour	Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Borislava I. Simidchieva, Lori A. Clarke, Leon J. Osterweil	Representing Process Variation with a Process Family.	ICSP	2007	DBLP DOI BibTeX RDF	process families, process variants, process instance generation, software product lines, process variation
2	Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang	Principle Hessian direction based parameter reduction with process variation.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Jung Hwan Choi, Jayathi Murthy, Kaushik Roy	The effect of process variation on device temperature in FinFET circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai	DFM/DFY practices during physical designs for timing, signal integrity, and power.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, DFY, dynamic IR drop, process variation, physical designs, DFM, design for manufacturability, signal integrity, timing integrity, yield analysis, design for yield
2	T. M. Mak, Sani R. Nassif	Guest Editors' Introduction: Process Variation and Stochastic Design and Test.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	silicon manufacturing processes, adaptive circuits, process variation, process monitoring, subthreshold leakage
2	Ke Meng, Russ Joseph	Process variation aware cache leakage management.	ISLPED	2006	DBLP DOI BibTeX RDF	gated-VDD, selective cache ways, low power, process variation, leakage, cache management
2	Xiaoyao Liang, David Brooks	Microarchitecture parameter selection to optimize system performance under process variation.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Jinjun Xiong, Vladimir Zolotov, Lei He	Robust extraction of spatial correlation.	ISPD	2006	DBLP DOI BibTeX RDF	robust extraction, process variation, extraction, spatial correlation
2	Kunhyuk Kang, Bipul C. Paul, Kaushik Roy	Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Process variation, spatial correlation, statistical timing analysis
2	Bipul C. Paul, Kaushik Roy	Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	adaptive body bias design, statistical analysis, process variation, delay fault testing
2	Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi	Longest-path selection for delay test under process variation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Rasit Onur Topaloglu, Alex Orailoglu	A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs.	DAC	2005	DBLP DOI BibTeX RDF
2	Jeng-Liang Tsai, Charlie Chung-Ping Chen	Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Fang Liu, Sule Ozev	Hierarchical analysis of process variation for mixed-signal systems.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Osama Neiroukh, Xiaoyu Song	Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques.	DATE	2005	DBLP DOI BibTeX RDF
2	Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy	Process Variation Tolerant Online Current Monitor for Robust Systems.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu	Skew scheduling and clock routing for improved tolerance to process variations.	ASP-DAC	2005	DBLP DOI BibTeX RDF	layout embedding, skew scheduling, reliability, process variation, clock routing
2	Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy	Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	process variation, yield, leakage, dual-Vt, metal gate
2	Siva Narendra	Challenges and design choices in nanoscale CMOS.	JETC	2005	DBLP DOI BibTeX RDF	nanoscale, process variation, CMOS, leakage power
2	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy	Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.	VTS	2005	DBLP DOI BibTeX RDF	Failure mechanixm, Process Variation, DFT, SRAM, March Test
2	Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi	PARADE: PARAmetric Delay Evaluation under Process Variation.	ISQED	2004	DBLP DOI BibTeX RDF
2	Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy	Novel sizing algorithm for yield improvement under process variation in nanometer technology.	DAC	2004	DBLP DOI BibTeX RDF	Performance, Design, Algorithms, Reliability
2	Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi	Longest path selection for delay test under process variation.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Ashish Srivastava, Dennis Sylvester	A general framework for probabilistic low-power design space exploration considering process variation.	ICCAD	2004	DBLP DOI BibTeX RDF
2	Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy	Leakage in nano-scale technologies: mechanisms, impact and design considerations.	DAC	2004	DBLP DOI BibTeX RDF	process variation, leakage current, circuit design
2	T. Chen, S. Naffziger	Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Bing Lu, Jiang Hu, Gary Ellis, Haihua Su	Process variation aware clock tree routing.	ISPD	2003	DBLP DOI BibTeX RDF	VLSI, interconnect, physical design, clock tree synthesis
2	Zhuo Li, Xiang Lu, Weiping Shi	Process variation dimension reduction based on SVD.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Ron Wilson, Siva Narendra, Vivek De	Evening Panel Discussion: Process Variation: Is It Too Much to Handle? (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
2	Yavuz Kiliç, Mark Zwolinski	Process variation independent built-in current sensor for analogue built-in self-test.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda	High speed IDDQ test and its testability for process variation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing
1	Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Che-Wei Wu, Chia-Chen Kuo, Pi-Feng Chiu, Yih-Shan Yang, Yu-Sheng Chen, Heng-Yuan Lee, Chen-Hsin Lien, Frederick T. Chen, Keng-Li Su, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai	A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.	J. Solid-State Circuits	2013	DBLP DOI BibTeX RDF