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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 12 occurrences of 12 keywords
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Results
Found 9 publication records. Showing 9 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kazuhito Ito, Keisuke Nasu |
A Processor Accelerator for Software Decoding of Reed-Solomon Codes.  |
IEICE Transactions  |
2012 |
DBLP BibTeX RDF |
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| 1 | Kang Zhao, Jinian Bian |
Processor Accelerator Customization through Data Flow Graph Exploration.  |
IEICE Transactions  |
2011 |
DBLP BibTeX RDF |
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| 1 | Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski |
LegUp: high-level synthesis for FPGA-based processor/accelerator systems.  |
FPGA  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula |
Enabling Multithreading on CGRAs.  |
ICPP  |
2011 |
DBLP DOI BibTeX RDF |
CGRA, processor accelerator, dynamic threading, runtime scheduling, page-based mapping, CGRA mapping technique, low power, multithreading, compiler optimization, scheduling technique |
| 1 | Kazuhito Ito |
A Processor Accelerator for Software Decoding of BCH Codes.  |
IEICE Transactions  |
2010 |
DBLP BibTeX RDF |
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| 1 | Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux |
Vector Processing as a Soft Processor Accelerator.  |
TRETS  |
2009 |
DBLP DOI BibTeX RDF |
parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor |
| 1 | Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig |
Performance and power of cache-based reconfigurable computing.  |
ISCA  |
2009 |
DBLP DOI BibTeX RDF |
c-to-gates, c-to-hardware, co-processor accelerator, many-cache, synthesis compiler, fpga, caches |
| 1 | Sadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith |
An Application Specific Memory Characterization Technique for Co-processor Accelerators.  |
ASAP  |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Gokhan Memik, Seda Ogrenci Memik, William H. Mangione-Smith |
Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic.  |
FCCM  |
2002 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #9 of 9 (100 per page; Change: )
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