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Searching for phrase processor accelerator (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
2002-2012 (9)
Publication types (Num. hits)
article(4) inproceedings(5)
Venues (Conferences, Journals, ...)
IEICE Transactions(3) ASAP(1) FCCM(1) FPGA(1) ICPP(1) ISCA(1) TRETS(1)
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Results
Found 9 publication records. Showing 9 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Kazuhito Ito, Keisuke Nasu A Processor Accelerator for Software Decoding of Reed-Solomon Codes. Search on Bibsonomy IEICE Transactions The full citation details ... 2012 DBLP  BibTeX  RDF
1Kang Zhao, Jinian Bian Processor Accelerator Customization through Data Flow Graph Exploration. Search on Bibsonomy IEICE Transactions The full citation details ... 2011 DBLP  BibTeX  RDF
1Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski LegUp: high-level synthesis for FPGA-based processor/accelerator systems. Search on Bibsonomy FPGA The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula Enabling Multithreading on CGRAs. Search on Bibsonomy ICPP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF CGRA, processor accelerator, dynamic threading, runtime scheduling, page-based mapping, CGRA mapping technique, low power, multithreading, compiler optimization, scheduling technique
1Kazuhito Ito A Processor Accelerator for Software Decoding of BCH Codes. Search on Bibsonomy IEICE Transactions The full citation details ... 2010 DBLP  BibTeX  RDF
1Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux Vector Processing as a Soft Processor Accelerator. Search on Bibsonomy TRETS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor
1Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig Performance and power of cache-based reconfigurable computing. Search on Bibsonomy ISCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF c-to-gates, c-to-hardware, co-processor accelerator, many-cache, synthesis compiler, fpga, caches
1Sadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith An Application Specific Memory Characterization Technique for Co-processor Accelerators. Search on Bibsonomy ASAP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Gokhan Memik, Seda Ogrenci Memik, William H. Mangione-Smith Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic. Search on Bibsonomy FCCM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
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