Search results for "processor performance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	Understanding the effects of wrong-path memory references on processor performance.	WMPI	2004	DBLP DOI BibTeX RDF	processor performance analysis, wrong path modeling, wrong-path memory references, speculative execution, data prefetching, execution-driven simulation, cache pollution
2	Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang 0003, Mark Horowitz	Processor Performance Modeling using Symbolic Simulation.	ISPASS	2008	DBLP DOI BibTeX RDF
2	Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum	Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.	DAC	2008	DBLP DOI BibTeX RDF	dynamic resizing, performance, embedded processor, register file
2	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith	A Top-Down Approach to Architecting CPI Component Performance Counters.	IEEE Micro	2007	DBLP DOI BibTeX RDF	hardware performance counter architecture, superscalar processor performance modeling, performance, measurement, experimentation, modeling techniques
2	Toshinori Sato, Akihiro Chiyonobu	Evaluating the Impact of Fault Recovery on Superscalar Processor Performance.	PRDC	2006	DBLP DOI BibTeX RDF
2	Jiangjiang Liu, Brian Bell, Tan Truong	Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance.	IMSCCS	2006	DBLP DOI BibTeX RDF
2	P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil	Construction and use of linear regression models for processor performance analysis.	HPCA	2006	DBLP DOI BibTeX RDF
2	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith	A performance counter architecture for computing accurate CPI components.	ASPLOS	2006	DBLP DOI BibTeX RDF	hardware performance counter architecture, superscalar processor performance modeling
2	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor performance modeling, speculative execution, runahead execution, Single data stream architectures
2	Eric Sprangle, Doug Carmean	Increasing Processor Performance by Implementing Deeper Pipelines. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	Pipeline depth, Pipeline
2	David Parello, Olivier Temam, Jean-Marie Verdun	On increasing architecture awareness in program optimizations to bridge the gap between peak and sustained processor performance: matrix-multiply revisited.	SC	2002	DBLP DOI BibTeX RDF
2	Derek B. Noonburg, John Paul Shen	A Framework for Statistical Modeling of Superscalar Processor Performance.	HPCA	1997	DBLP DOI BibTeX RDF
2	Paul F. Stelling, Vojin G. Oklobdzija	Implementing Multiply-Accumulate Operation in Multiplication Time.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed
2	Jian Chen, Valerie E. Taylor	PART: a partitioning tool for efficient use of distributed systems.	ASAP	1997	DBLP DOI BibTeX RDF	partitioning tool, geographically distributed supercomputers interconnection, decomposition tool, finite element based problems, performance, distributed systems, computational complexity, computational complexity, simulated annealing, wide area network, high-speed networks, execution time, processor performance, PART
2	Peggy B. K. Pang, Mark R. Greenstreet	Self-Timed Meshes Are Faster Than Synchronous.	ASYNC	1997	DBLP DOI BibTeX RDF	self-timed meshes, linear speed-up, per-processor performance, simulation, logic CAD
2	Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh	The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors.	HPCA	1996	DBLP DOI BibTeX RDF	shared-cache clustering, small-scale shared-memory multiprocessors, shared global bus, low-latency interconnections, performance evaluation, shared memory systems, cache storage, memory system, multichip module, L2 cache, processor performance, high-bandwidth, bus contention
2	Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye	A technique to determine power-efficient, high-performance superscalar processors.	HICSS	1995	DBLP DOI BibTeX RDF	high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation
2	Derek B. Noonburg, John Paul Shen	Theoretical modeling of superscalar processor performance.	MICRO	1994	DBLP DOI BibTeX RDF
2	Yen-Jen Oyang	Exploiting multi-way branching to boost superscalar processor performance.	SIGPLAN Notices	1991	DBLP DOI BibTeX RDF
1	William Lloyd Bircher, Lizy K. John	Complete System Power Estimation Using Processor Performance Events.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
1	Vijay Janapa Reddi, David Brooks	Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Stijn Eyerman, Kenneth Hoste, Lieven Eeckhout	Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware.	ISPASS	2011	DBLP DOI BibTeX RDF
1	Zhitao Wan	A Dynamic Core Grouping Approach to Improve Raw Architecture Many-core Processor Performance.	PARELEC	2011	DBLP DOI BibTeX RDF
1	José Carlos Sancho, Michael Lang 0003, Darren J. Kerbyson	Analyzing the trade-off between multiple memory controllers and memory channels on multi-core processor performance.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Stijn Eyerman, Lieven Eeckhout	Probabilistic job symbiosis modeling for SMT processor scheduling.	ASPLOS	2010	DBLP DOI BibTeX RDF	simultaneous multi-threading (smt), symbiotic job scheduling, performance modeling
1	Arquimedes Canedo, Takeo Yoshizawa, Hideaki Komatsu	Automatic parallelization of simulink applications.	CGO	2010	DBLP DOI BibTeX RDF	coarse grain dataflow, equation-level parallelism, compilers, multi-core, automatic parallelization, simulink, strands
1	Victor Pankratius, Walter F. Tichy, Peter Hinsbeeck	Multicore software engineering: the next challenge in software engineering.	ICSE	2010	DBLP DOI BibTeX RDF
1	Mehmet Basoglu, Michael Orshansky, Mattan Erez	NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime.	ISLPED	2010	DBLP DOI BibTeX RDF	wearout, energy efficiency, process variation, DVFS, NBTI
1	Jungwoo Ha, Stephen P. Crago	Opportunities for concurrent dynamic analysis with explicit inter-core communication.	PASTE	2010	DBLP DOI BibTeX RDF	inter-core communication, concurrency, dynamic analysis, instrumentation
1	David A. Patterson	Software knows best: portable parallelism requires standardized measurements of transparent hardware.	WOSP/SIPEW	2010	DBLP DOI BibTeX RDF	standardized
1	Bin Li, Lu Peng, Balachandran Ramadass	Accurate and efficient processor performance prediction via regression tree based modeling.	Journal of Systems Architecture - Embedded Systems Design	2009	DBLP DOI BibTeX RDF
1	Kenneth Hoste, Lieven Eeckhout	A Methodology for Analyzing Commercial Processor Performance Numbers.	IEEE Computer	2009	DBLP DOI BibTeX RDF	computer architecture modeling, system performance, computer systems organization
1	Marina Biberstein, S. Dori-Hacohen, Yuval Harel, Andre Heilper, Bilha Mendelson, Uzi Shvadron, E. Treister, Javier Turek, Moon S. Chang	Cell Broadband Engine processor performance optimization: Tracing tools implementation and use.	IBM Journal of Research and Development	2009	DBLP DOI BibTeX RDF
1	Kiyeon Lee, Shayne Evans, Sangyeun Cho	Accurately approximating superscalar processor performance from traces.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Yangyang Pan, Tong Zhang	Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking.	ASAP	2009	DBLP DOI BibTeX RDF
1	Tomas Tuma, Sean Rooney, Paul Hurley	On the Applicability of Compressive Sampling in Fine Grained Processor Performance Monitoring.	ICECCS	2009	DBLP DOI BibTeX RDF
1	Lide Duan, Bin Li, Lu Peng	Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics.	HPCA	2009	DBLP DOI BibTeX RDF
1	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	Hybrid multithreading for VLIW processors.	CASES	2009	DBLP DOI BibTeX RDF	multithreading, clustered VLIW processors
1	Weili Li, Lixin Yu	Efficient line buffer instruction cache scheme with prefetch.	Int. Conf. Interaction Sciences	2009	DBLP DOI BibTeX RDF	line buffer, cache, prefetch
1	Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Characterizing the resource-sharing levels in the UltraSPARC T2 processor.	MICRO	2009	DBLP DOI BibTeX RDF	Sun Nigara T2, CMP, job scheduling, simultaneous multithreading, performance characterization, CMT
1	Wenjing Ma, Gagan Agrawal	A compiler and runtime system for enabling data mining applications on gpus.	PPOPP	2009	DBLP DOI BibTeX RDF	data mining, gpgpu, cuda
1	Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, Robert S. Schreiber	Future scaling of processor-memory interfaces.	SC	2009	DBLP DOI BibTeX RDF
1	Constantine Bekas, Alessandro Curioni, I. Fedulova	Low cost high performance uncertainty quantification.	SC-WHPCF	2009	DBLP DOI BibTeX RDF	inverse covariance matrices, quadratic cost, stochastic estimation, massive parallelism, iterative solvers, iterative refinement
1	Dinesh K. Kaushik, Micheal Smith, Allan B. Wollaber, Barry F. Smith, Andrew Siegel, Won Sik Yang	Enabling high-fidelity neutron transport simulations on petascale architectures.	SC	2009	DBLP DOI BibTeX RDF	discrete ordinates, neutron transport, nuclear reactors, parallel scalability, memory bandwidth
1	Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim	Age based scheduling for asymmetric multiprocessors.	SC	2009	DBLP DOI BibTeX RDF	age based scheduling, asymmetric multiprocessors, thread scheduling
1	Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles	Blueshift: Designing processors for timing speculation from the ground up.	HPCA	2009	DBLP DOI BibTeX RDF
1	Samantika Subramaniam, Anne Bracy, Hong Wang 0003, Gabriel H. Loh	Criticality-based optimizations for efficient load processing.	HPCA	2009	DBLP DOI BibTeX RDF
1	Henning Klein, Jörg Keller	Storage architecture with integrity, redundancy and encryption.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería	On reducing misspeculations in a pipelined scheduler.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Toshinori Sato, Shingo Watanabe	Uncriticality-directed scheduling for tackling variation and power challenges.	ISQED	2009	DBLP DOI BibTeX RDF
1	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero	DIA: A Complexity-Effective Decoding Architecture.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro	Dynamically Adapted Low Power ASIPs.	ARC	2009	DBLP DOI BibTeX RDF
1	Pradeep Rao, Kazuaki Murakami	Empirical Performance Models for Java Workloads.	ARCS	2009	DBLP DOI BibTeX RDF
1	Michael Perrone	Multicore Programming Challenges.	Euro-Par	2009	DBLP DOI BibTeX RDF
1	John L. Henning	SPECrate2006: Alternatives Considered, Lessons Learned.	SPEC Benchmark Workshop	2009	DBLP DOI BibTeX RDF
1	Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle	Exploring and predicting the architecture/optimising compiler co-design space.	CASES	2008	DBLP DOI BibTeX RDF	architecture/compiler co-design, performance prediction, design-space exploration
1	Subhash Saini, Dennis C. Jespersen, Dale Talcott, M. Jahed Djomehri, Timothy Sandstrom	Application-based early performance evaluation of SGI altix 4700 systems for SGI systems.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	sgi altix 4700, performance analysis, benchmarking, supercomputing
1	Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon	Speculative DMA for architecturally visible storage in instruction set extensions.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	architecturally visible storage, speculative direct memory access, instruction set extensions, application-specific processors
1	Bryan C. Catanzaro, Kurt Keutzer, Bor-Yiing Su	Parallelizing CAD: a timely research agenda for EDA.	DAC	2008	DBLP DOI BibTeX RDF	parallelization, framework, pattern, manycore
1	Ehsan Atoofian, Amirali Baniasadi	Exploiting program cyclic behavior to reduce memory latency in embedded processors.	SAC	2008	DBLP DOI BibTeX RDF	high-speed embedded processors, row buffer, memory
1	Bin Li, Lu Peng, Balachandran Ramadass	Efficient mart-aided modeling for microarchitecture design space exploration and performance prediction.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	MART-aided models, performance prediction, design space exploration
1	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
1	David Slogsnat, Alexander Giese, Mondrian Nüssle, Ulrich Brüning	An open-source HyperTransport core.	TRETS	2008	DBLP DOI BibTeX RDF	HTX, HyperTransport, FPGA, prototyping, RTL
1	Frank Reichenbach, Dominik Lieckfeldt, Dirk Timmermann	Using QR-Updating with Reduced Complexity for Precise Localization in Mobile Sensor Networks.	CNSR	2008	DBLP DOI BibTeX RDF	localization, positioning, mobile sensor networks
1	Yu Zhou, Hui Guo	Application Specific Low Power ALU Design.	EUC	2008	DBLP DOI BibTeX RDF
1	Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt	Performance-aware speculation control using wrong path usefulness prediction.	HPCA	2008	DBLP DOI BibTeX RDF
1	Michael Kadin, Sherief Reda	Frequency and voltage planning for multi-core processors under thermal constraints.	ICCD	2008	DBLP DOI BibTeX RDF
1	Yong Chen, Surendra Byna, Xian-He Sun, Rajeev Thakur, William Gropp	2008 International Conference on Parallel Processing September 8-12, 2008 Portland, Oregon Exploring Parallel I/O Concurrency with Speculative Prefetching.	ICPP	2008	DBLP DOI BibTeX RDF
1	Subhash Saini, Dennis C. Jespersen, Dale Talcott, M. Jahed Djomehri, Timothy Sandstrom	Performance comparison of SGI Altix 4700 and SGI Altix 3700 Bx2.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Resit Sendag, Joshua J. Yi, Peng-fei Chuang, David J. Lilja	Low power/area branch prediction using complementary branch predictors.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Toshinori Sato, Shingo Watanabe	Instruction Scheduling for Variation-Originated Variable Latencies.	ISQED	2008	DBLP DOI BibTeX RDF	variable latency adder, long latency adder, instruction criticality, microprocessors, parameter variations
1	Wanessa Pereira Dias, Emilia Colonese	Performance Analysis of Cache and Scratchpad Memory in an Embedded High Performance Processor.	ITNG	2008	DBLP DOI BibTeX RDF	performance, cache, memory
1	Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas	EVAL: Utilizing processors with variation-induced timing errors.	MICRO	2008	DBLP DOI BibTeX RDF
1	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Modeling techniques, Pipeline processors, Modeling of computer architecture
1	Stijn Eyerman, Lieven Eeckhout, James E. Smith	Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Jerry Backer	The effect of memory bandwidth on processor performance.	Richard Tapia Celebration of Diversity in Computing Conference	2007	DBLP DOI BibTeX RDF
1	Viswanathan Subramanian, Mikel Bezdek, Naga Durga Prasad Avirneni, Arun K. Somani	Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning.	DSN	2007	DBLP DOI BibTeX RDF	overclocking, Reliability, Fault-Tolerant Computing, Dynamic, Superscalar processor
1	Jianxun Jason Ding, Abdul Waheed	Dual Processor Performance Characterization for XML Application-Oriented Networking.	ICPP	2007	DBLP DOI BibTeX RDF
1	Kenneth Hoste, Lieven Eeckhout, Hendrik Blockeel	Analyzing commercial processor performance numbers for predicting performance of applications of interest.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	benchmark similarity, performance analysis, performance prediction
1	George Lawton	The Next Big Thing in Chipmaking.	IEEE Computer	2007	DBLP DOI BibTeX RDF	chipmaking, processor performance
1	Juan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras	Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	leakage, value prediction, energy efficient architectures, cache decay
1	Jung Ho Ahn, Mattan Erez, William J. Dally	Tradeoff between data-, instruction-, and thread-level parallelism in stream processors.	ICS	2007	DBLP DOI BibTeX RDF	ILP, TLP, stream processors, aspect ratio, DLP
1	Jean Christophe Beyler, Philippe Clauss	Performance driven data cache prefetching in a dynamic software optimization system.	ICS	2007	DBLP DOI BibTeX RDF	binary instrumentation, data cache prefetching, dynamic optimization
1	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang	Thermal modeling and management of DRAM memory systems.	ISCA	2007	DBLP DOI BibTeX RDF	thermal management, thermal modeling, DRAM memories
1	Parry Husbands, Katherine A. Yelick	Multi-threading and one-sided communication in parallel LU factorization.	SC	2007	DBLP DOI BibTeX RDF	multithreading, latency tolerance, dense linear algebra
1	Arun Kejariwal, Gerolf Hoflehner, Darshan Desai, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum	Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	SPEC CPU benchmarks, performance evaluation, caches, branch prediction
1	Jan Staschulat, Rolf Ernst	Scalable precision cache analysis for real-time software.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	embedded systems, cache, Worst-case execution time analysis, preemptive scheduling
1	Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng	A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture.	ASAP	2007	DBLP DOI BibTeX RDF
1	Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.	ASP-DAC	2007	DBLP DOI BibTeX RDF	graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining
1	Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato	Indirect Tag Search Mechanism for Instruction Window Energy Reduction.	CIT	2007	DBLP DOI BibTeX RDF
1	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MLP-Aware Dynamic Cache Partitioning.	PACT	2007	DBLP DOI BibTeX RDF
1	Eric E. Aubanel, Xiaochen Wu	Incorporating Latency in Heterogeneous Graph Partitioning.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Juan M. Cebrian, Juan L. Aragón, José M. García	Leakage Energy Reduction in Value Predictors through Static Decay.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Ananth Devulapalli, Pete Wyckoff	File Creation Strategies in a Distributed Metadata File System.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Karthikeyan Vaidyanathan, Wei Huang, Lei Chai, Dhabaleswar K. Panda	Designing Efficient Asynchronous Memory Operations Using Hardware Copy Engine: A Case Study with I/OAT.	IPDPS	2007	DBLP DOI BibTeX RDF
1	William Lloyd Bircher, Lizy K. John	Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events.	ISPASS	2007	DBLP DOI BibTeX RDF	power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model
1	Niti Madan, Rajeev Balasubramonian	Leveraging 3D Technology for Improved Reliability.	MICRO	2007	DBLP DOI BibTeX RDF	redundant multi-threading, 3D die-stacking, dynamic timing errors, power-efficient microarchitecture, on-chip temperature, reliability, soft errors, parameter variation
1	Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger	Implementation and Evaluation of a Dynamically Routed Processor Operand Network.	NOCS	2007	DBLP DOI BibTeX RDF
1	Shuming Chen, Xiao Hu, Biwei Liu, Jihua Chen	An On-Line Control Flow Checking Method for VLIW Processor.	PRDC	2007	DBLP DOI BibTeX RDF
1	Hung-Chuan Lai, Shi-Jinn Horng, Yong-Yuan Chen, Pingzhi Fan, Yi Pan	A New Concurrent Detection of Control Flow Errors Based on DCT Technique.	PRDC	2007	DBLP DOI BibTeX RDF