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Searching for phrase processor processing time (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1992 (1)
Publication types (Num. hits)
article(1)
Venues (Conferences, Journals, ...)
IEEE Trans. Parallel Distrib. ...(1)
Authors
C. Y. Roger Chen(1) Shuo-Hsien Hsiao(1)
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Hits ?▲ Authors Title Venue Year Link Author keywords
2Shuo-Hsien Hsiao, C. Y. Roger Chen Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF message size, circuit switched multistage interconnection networks, hold strategy, processor-memory communications, processor processing time, closed queuing network model, performance evaluation, performance evaluation, multiprocessor interconnection networks, queueing theory, multiprocessor systems, switching theory, memory access
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