Search results for "processors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Pawel Gepner, David L. Fraser, Michal Filip Kowalik	Performance Evolution and Power Benefits of Cluster System Utilizing Quad-Core and Dual-Core Intel Xeon Processors.	PPAM	2007	DBLP DOI BibTeX RDF	dual-core processors, quad-core processors, parallel processing, benchmarks, HPC, multi-core processors
5	Ruby B. Lee	Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures.	ASAP	2000	DBLP DOI BibTeX RDF	microSIMD, multimedia, microprocessors, computer arithmetic, permutations, processors, digital signal processors, Instruction Set Architecture, fine-grain parallelism, subword parallelism, media processors
5	Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park	Scheduling of conditional branches using SSA form for superscalar/VLIW processors. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	conditional branches scheduling, very long instruction word processors, compensation code, optimization, computational complexity, complexity, parallel architectures, processor scheduling, superscalar processors, instruction sets, instruction set, VLIW processors, code motion, global scheduling, conditional branches, SSA
5	Michael Yang, Ahmed N. Tantawy	A design methodology for protocol processors.	FTDCS	1995	DBLP DOI BibTeX RDF	protocol processors, FCS, Fibre Channel Standard, homogeneous multi-processors, single VLSI chip, VHDL macro libraries, VLSI protocol processors, CVDS, Communication VLSI Design System, protocols, asynchronous transfer mode, ATM, multiprocessing systems, communication protocols
5	Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang	VLSI design of densely-connected array processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets
4	Pawel Gepner, David L. Fraser, Michal Filip Kowalik	Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications.	ICCS	2008	DBLP DOI BibTeX RDF	quad-core processors, parallel processing, benchmarks, HPC, multi-core processors
4	David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky	Conjoining soft-core FPGA processors.	ICCAD	2006	DBLP DOI BibTeX RDF	conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning
4	Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero	Kilo-Instruction Processors: Overcoming the Memory Wall.	IEEE Micro	2005	DBLP DOI BibTeX RDF	in-flight instructions, ROB, superscalar processors, memory wall, issue queue, Kilo-instruction processors
4	Stephen W. Melvin, Yale N. Patt	Handling of packet dependencies: a critical issue for highly parallel network processors.	CASES	2002	DBLP DOI BibTeX RDF	memory synchronization, packet dependencies, parallel processing, network processors, processor architecture, thread level speculation, multithreaded processors, packet processing
4	M. Watheq El-Kharashi, Fayez El Guibaly, Kin F. Li	Adapting Tomasulo's algorithm for bytecode folding based Java processors.	SIGARCH Computer Architecture News	2001	DBLP DOI BibTeX RDF	instruction shelving, java bytecode folding, java stack folding, reservation stations, stack processors, tomasulo's algorithm, java, Java, java virtual machine, dynamic scheduling, java processors, register renaming
4	Stefan M. Petters	Bounding the execution time of real-time tasks on modern processors.	RTCSA	2000	DBLP DOI BibTeX RDF	task execution time, modern processors, embedded hard real time systems, up-to-date processors, fast core frequency, systematic information, real-time systems, computer architecture, complex systems, control flow graph, main memory, flow graphs, optimising compilers, real time tasks, acceleration techniques
4	Nuno Roma, Leonel Sousa	In the Development and Evaluation of Specialized Processors for Computing High-Order 2-D Image Moments in Real-Time.	CAMP	2000	DBLP DOI BibTeX RDF	specialized processors, high-order 2-D image moments, computational intensive task, systolic processing, programmable digital processors, configurable hardware logic, real-time system, image analysis, object modelling, floating-point arithmetic, digital signal processing chips, object matching
4	Fuji Ren	Dialogue Machine Translation System Using Multiple Translation Processors. (PDF / PS)	DEXA Workshops	2000	DBLP DOI BibTeX RDF	dialogue machine translation system, multiple translation processors, natural dialogues, irregular expressions, natural conversation, ill-formed sentences, dialogue machine translation, MTP, translation processors, original language analysis, target language generation processing, Robust Parser based Translation Processor, Example Based Translation Processor, Family Modal based Translation Processor, Super Function based Translation Processor, information analysis model, syntactic constraint analysis model, semantic constraint analysis model, robust dialogue translation, language translation
4	Pedro Marcuello, Antonio González	Clustered speculative multithreaded processors.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF	control-flow speculation, data value speculation, simultaneous multithreaded processors, dynamically scheduled processors, data dependance speculation, clustered processors
4	Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith	Trace Processors.	MICRO	1997	DBLP BibTeX RDF	trace processors, multiscalar processors, next trace prediction, selective reissuing, context-based value prediction, trace cache
4	Bernard Goossens, Duc Thang Vu	Multithreading to Improve Cycle Width and CPI in Superpipelined Superscalar Processors.	ISPAN	1996	DBLP DOI BibTeX RDF	Superpipelined Processors, Architecture, Instruction Level Parallelism, Superscalar Processors, Multithreaded Processors
4	Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu	Analysis, evaluation, and comparison of algorithms for scheduling task graphs on parallel processors.	ISPAN	1996	DBLP DOI BibTeX RDF	edge-weighted directed acyclic graph, bounded number of processors scheduling, arbitrary processor network, scheduling, scheduling, parallel programming, processor scheduling, data flow graphs, task graphs, parallel processors, dataflow graph
4	Wade Walker, Harvey G. Cragon	Interrupt Processing in Concurrent Processors.	IEEE Computer	1995	DBLP DOI BibTeX RDF	Interrupt processing, imprecise interrupts, concurrent processors, checkpointing, taxonomy, superscalar processors, pipelined processors, out- of-order execution, out-of-order issue, precise interrupts
4	B. Saha, J. Sukarno Mertoguno, Nikolaos G. Bourbakis	The VLSI design and implementation of the array processors of a multilayer vision system architecture.	ASAP	1995	DBLP DOI BibTeX RDF	multilayer vision system architecture, KYDON vision system, multilayered image understanding system, computer vision, parallel processing, VLSI, digital simulation, VLSI design, array processors, timing simulation
4	Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye	A technique to determine power-efficient, high-performance superscalar processors.	HICSS	1995	DBLP DOI BibTeX RDF	high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation
4	Santanu Dutta, Wayne Wolf, Andrew Wolfe	VLSI issues in memory-system design for video signal processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	VLSI issues, video signal processors, memory-system architectures, circuit-level issues, register-cache based hierarchy, general-purpose programmable microprocessors, VLSI, system architecture, utilization, memory architecture, memory architecture, video signal processing, area, cycle time, memory-system design
4	Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang	A self-timed redundant-binary number to binary number converter for digital arithmetic processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	convertors, self-timed redundant-binary number to binary number converter, digital arithmetic processors, self-timed converter circuit, variable conversion time, statistical upper bound, delays, digital arithmetic, propagation delay, redundant number systems
4	John-David Wellman, Edward S. Davidson	The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	resource conflict methodology, early-stage design space exploration, superscalar RISC processors, execution trace driven simulation, hardware element model, analysis program, performance evaluation, virtual machines, computer architecture, reduced instruction set computing, design cycle
4	Anurag Gupta, Ian F. Akyildiz, Richard Fujimoto	Performance Analysis of Time Warp With Multiple Homogeneous Processors.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	interacting processors, Time Warp protocol, discrete-state, continuous-time Markov chain model, exponential task times, timestamp increments, event message, negligible rollback, unbounded message buffers, homogeneous processors, processed events, rollback probability, uncommitted processed events, Time Warp testbed, performance evaluation, protocols, discrete event simulation, Markov processes, performance measures, multiprocessing systems, shared-memory multiprocessor, parallel simulation, speedup, communication delay, virtual time, state saving, probability mass function, probability distribution function
3	Sergey Zhuravlev, Sergey Blagodurov, Alexandra Fedorova	Addressing shared resource contention in multicore processors via scheduling.	ASPLOS	2010	DBLP DOI BibTeX RDF	shared resource contention, scheduling, multicore processors
3	Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras	Interval-based models for run-time DVFS orchestration in superscalar processors.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	performance and power modeling, superscalar out-of-order processors, dynamic voltage and frequency scaling
3	Ning Weng, Tilman Wolf	Analytic modeling of network processors for parallel workload mapping.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	embedded systems, network processors, multiprocessor scheduling, Application profiling
3	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith	A mechanistic performance model for superscalar out-of-order processors.	ACM Trans. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling
3	Teemu Pitkänen, Jarno K. Tanskanen, Risto Mäkinen, Jarmo Takala	Parallel Memory Architecture for Application-Specific Instruction-Set Processors.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	TTA, Transport triggered architecture, Low power, ASIP, Application-specific instruction-set processors, Parallel memory
3	Surendra Byna, Yong Chen, Xian-He Sun	Taxonomy of Data Prefetching for Multicore Processors.	J. Comput. Sci. Technol.	2009	DBLP DOI BibTeX RDF	taxonomy of prefetching strategies, memory hierarchy, multicore processors, data prefetching
3	Jinho Suh, Michel Dubois	Dynamic MIPS rate stabilization in out-of-order processors.	ISCA	2009	DBLP DOI BibTeX RDF	ooo processors, real-time systems, embedded systems, stabilization, variability
3	Andrew D. Hilton, Amir Roth	Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors.	ISCA	2009	DBLP DOI BibTeX RDF	checkpoint processors, load-store queues
3	Philippe Moret, Walter Binder, Alex Villazón	CProf: customizable calling context cross-profiling for embedded java processors.	PEPM	2009	DBLP DOI BibTeX RDF	cross-profiling, embedded java processors, java virtual machine, bytecode instrumentation
3	Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha	Throughput optimal task allocation under thermal constraints for multi-core processors.	DAC	2009	DBLP DOI BibTeX RDF	optimal throughput, task allocation, thermal management, multi-core processors, thread migration
3	Manoj Gupta 0001, Fermín Sánchez, Josep Llosa	Hybrid multithreading for VLIW processors.	CASES	2009	DBLP DOI BibTeX RDF	multithreading, clustered VLIW processors
3	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Modeling techniques, Pipeline processors, Modeling of computer architecture
3	Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy	Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Variable-cycle functional unit, speed binning, Scheduling, process variation, Superscalar Processors
3	Fadi N. Sibai	Evaluating the performance of single and multiple core processors with PCMARK®05 and benchmark analysis.	SIGMETRICS Performance Evaluation Review	2008	DBLP DOI BibTeX RDF	performance benchmark, single and dual core processors, workload characterization
3	Vahid Kazempour, Alexandra Fedorova, Pouya Alagheband	Performance Implications of Cache Affinity on Multicore Processors.	Euro-Par	2008	DBLP DOI BibTeX RDF	cache affinity, scheduling, performance evaluation, multicore processors
3	Artiom Alhazov, Erzsébet Csuhaj-Varjú, Carlos Martín-Vide, Yurii Rogozhin	About Universal Hybrid Networks of Evolutionary Processors of Small Size.	LATA	2008	DBLP DOI BibTeX RDF	Hybrid networks of evolutionary processors, Small universal systems, Circular Post machines, Descriptional complexity, Bio-inspired computing
3	Bingsheng He, Wenbin Fang, Qiong Luo, Naga K. Govindaraju, Tuyong Wang	Mars: a MapReduce framework on graphics processors.	PACT	2008	DBLP DOI BibTeX RDF	GPGPU, MapReduce, data parallelism, graphics processor, multi-core processors, web analysis
3	Jayanth Gummaraju, Joel Coburn, Yoshio Turner, Mendel Rosenblum	Streamware: programming general-purpose multicore processors using streams.	ASPLOS	2008	DBLP DOI BibTeX RDF	general-purpose multicore processors, programming, streams, runtime system
3	Ya-shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao	Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques.	DAC	2008	DBLP DOI BibTeX RDF	subgraph covering, VLIW, ASIPs, extensible processors
3	Garo Bournoutian, Alex Orailoglu	Miss reduction in embedded processors through dynamic, power-friendly cache design.	DAC	2008	DBLP DOI BibTeX RDF	dynamic associativity, multi-core, embedded processors, data cache
3	Xuan Guan, Yunsi Fei	Reducing power consumption of embedded processors through register file partitioning and compiler support.	ASAP	2008	DBLP DOI BibTeX RDF
3	Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf	Buffer allocation for advanced packet segmentation in Network Processors.	ASAP	2008	DBLP DOI BibTeX RDF
3	Yedidya Hilewitz, Cédric Lauradoux, Ruby B. Lee	Bit matrix multiplication in commodity processors.	ASAP	2008	DBLP DOI BibTeX RDF
3	Walter Binder, Alex Villazón, Martin Schoeberl, Philippe Moret	Cache-aware cross-profiling for java processors.	CASES	2008	DBLP DOI BibTeX RDF	cross-profiling, embedded java processors, platform-independent dynamic metrics, bytecode instrumentation
3	Francisco D. Igual, Rafael Mayo, Enrique S. Quintana-Ortí	Attaining High Performance in General-Purpose Computations on Current Graphics Processors.	VECPAR	2008	DBLP DOI BibTeX RDF	general purpose computing on GPU, image processing, high performance, linear algebra, Graphics processors (GPUs)
3	Ronny Krashinsky, Christopher Batten, Krste Asanovic	Implementing the scale vector-thread processor.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	hybrid C++/Verilog simulation, iterative VLSI design flow, procedural datapath pre-placement, vector-thread processors, multithreaded processors, Vector processors
3	Christian Tenllado, Javier Setoain, Manuel Prieto, Luis Piñuel, Francisco Tirado	Parallel Implementation of the 2D Discrete Wavelet Transform on Graphics Processing Units: Filter Bank versus Lifting.	IEEE Trans. Parallel Distrib. Syst.	2008	DBLP DOI BibTeX RDF	Parallelprocessing, Paralleland vector implementations, Wavelets and fractals, Optimization, Parallel algorithms, Graphics processors, SIMD processors
3	Xiaotong Zhuang, Santosh Pande	Power-efficient prefetching for embedded processors.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	bit-differential addressing, offset assignment, embedded processors, Data prefetching
3	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low energy, loop buffers, VLIW processors
3	Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau	A predictive decode filter cache for reducing power consumption in embedded processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Cache, embedded processors, power optimization
3	Eduardo Tavares, Raimundo S. Barreto, Paulo Romero Martins Maciel, Meuse N. Oliveira Jr., Leonardo Amorim, Fernando Rocha, Ricardo Massa Ferreira Lima	Software synthesis for hard real-time embedded systems with multiple processors.	ACM SIGSOFT Software Engineering Notes	2007	DBLP DOI BibTeX RDF	petri nets, real-time embedded systems, software synthesis, multiple processors
3	Yogesh Gupta, Sriram Sethuraman	A Low Complexity Block-Based Video De-interlacing Algorithm for SIMD Processors.	PCM	2007	DBLP DOI BibTeX RDF	Interlaced, de-interlacing, pre-/post-processing, motion detection, spatio-temporal, progressive, SIMD processors, block-based
3	Tejas Karkhanis, James E. Smith	Automated design of application specific superscalar processors: an analytical approach.	ISCA	2007	DBLP DOI BibTeX RDF	performance model, analytical model, design optimization, energy model, application specific processors
3	Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti	Throughput of multi-core processors under thermal constraints.	ISLPED	2007	DBLP DOI BibTeX RDF	leakage dependence on temperature, throughput, power, speedup, thermal management, multi-core processors
3	Tiffany M. Mintz, James P. Davis	Low-power tradeoffs for mobile computing applications: embedded processors versus custom computing kernels.	ACM Southeast Regional Conference	2007	DBLP DOI BibTeX RDF	algorithmic state machine, low-power design, reconfigurable computing, embedded processors
3	Djakhongir Siradjev, JeongKi Park, Taesang Choi, Joonkyung Lee, Bong Dae Choi, Young-Tak Kim	10Gbps Scalable Flow Generation and Per-flow Control with Hierarchical Flow Aggregation & Decomposition Using IXP2800 Network Processors.	APNOMS	2007	DBLP DOI BibTeX RDF	flow monitoring, classification, control, network processors
3	Suman Mamidi, Michael J. Schulte, Daniel Iancu, C. John Glossner	Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication Systems.	ASAP	2007	DBLP DOI BibTeX RDF
3	Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara	Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors.	European Test Symposium	2007	DBLP DOI BibTeX RDF	Dynamically reconfigurable processors, optimal contexts, test frames, self-test, test application time
3	Zhiyong Yu, Zhiyi Yang, Fan Zhang, Zhiwen Yu, Tuanqing Zhang	Replication-Based Partial Dynamic Scheduling on Heterogeneous Network Processors.	APPT	2007	DBLP DOI BibTeX RDF	partial dynamic scheduling, scheduling, directed acyclic graph, network processors, task replication
3	Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-Ching Ju	A Throughput-Driven Task Creation and Mapping for Network Processors.	HiPEAC	2007	DBLP DOI BibTeX RDF	Intel IXP, Task Creation and Mapping, Throughput, Network Processors, Dataflow Programming
3	Remco Loos	On Accepting Networks of Splicing Processors of Size 3.	CiE	2007	DBLP DOI BibTeX RDF	Splicing, Networks of Processors, Molecular Computation
3	Roman L. Lysecky, Greg Stitt, Frank Vahid	Warp Processors.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	FPGA, dynamic optimization, hardware/software codesign, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation
3	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero	Predictable Performance in SMT Processors: Synergy between the OS and SMTs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	real time, operating systems, performance predictability, ILP, thread-level parallelism, simultaneous multithreading, Multithreaded processors
3	Naga K. Govindaraju, Scott Larsen, Jim Gray, Dinesh Manocha	Memory - A memory model for scientific algorithms on graphics processors.	SC	2006	DBLP DOI BibTeX RDF	scientific algorithms, graphics processors, memory model
3	Kaveh Jokar Deris, Amirali Baniasadi	Branchless cycle prediction for embedded processors.	SAC	2006	DBLP DOI BibTeX RDF	low-power design, embedded processors, branch target buffer, power-aware architectures
3	Xin Huang, Tilman Wolf	A methodology for evaluating runtime support in network processors.	ANCS	2006	DBLP DOI BibTeX RDF	runtime management, workload partitioning and mapping, network processors
3	Pablo Ituero, Marisa López-Vallejo	New Schemes in Clustered VLIW Processors Applied to Turbo Decoding.	ASAP	2006	DBLP DOI BibTeX RDF
3	Jeffrey M. Arnold	Software Configurable Processors.	ASAP	2006	DBLP DOI BibTeX RDF
3	Earl E. Swartzlander Jr.	Systolic FFT Processors: Past, Present and Future.	ASAP	2006	DBLP DOI BibTeX RDF
3	Feng Xian, Witawas Srisa-an, Hong Jiang	Evaluating Hardware Support for Reference Counting Using Software Configurable Processors.	ASAP	2006	DBLP DOI BibTeX RDF
3	Peter R. Cappello	Multicore processors as Array Processors: Research Opportunities.	ASAP	2006	DBLP DOI BibTeX RDF
3	Grant Martin	Recent Developments in Configurable and Extensible Processors.	ASAP	2006	DBLP DOI BibTeX RDF
3	Paolo Bonzini, Laura Pozzi	Code transformation strategies for extensible embedded processors.	CASES	2006	DBLP DOI BibTeX RDF	compilers, ASIPs, instruction-set extensions, customizable processors
3	Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven	Static cache partitioning robustness analysis for embedded on-chip multi-processors.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	robustness, cache partitioning, multi-processors
3	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Kilo-instruction processors, runahead and prefetching.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors
3	Geoff Lowney	Why Intel is designing multi-core processors.	SPAA	2006	DBLP DOI BibTeX RDF	multi-core processors
3	Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha	Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.	VLSI Design	2006	DBLP DOI BibTeX RDF	Performance, Embedded Systems, Security Protocols, Configurability, Extensibility, Embedded Processors, IPSec, Embedded Security
3	Xiaotong Zhuang, Santosh Pande	Effective thread management on network processors with compiler analysis.	LCTES	2006	DBLP DOI BibTeX RDF	real-time scheduling, compiler optimizations, network processors, CPU scheduling
3	Roshan G. Ragel, Sri Parameswaran	Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	embedded processor reliability, hardware/software technique, micro-instruction routines, preemptive fault detection, reliable processors, control flow checking
3	Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha	Architectural support for safe software execution on embedded processors.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	type safety, memory safety, extensible processors
3	John Oliver, Ravishankar Rao, Michael Brown, Jennifer Mankin, Diana Franklin, Frederic T. Chong, Venkatesh Akella	Tile size selection for low-power tile-based architectures.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	multi-core processors, media processors
3	J. S. H. van Leeuwaarden, Jacques Resing	A Tandem Queue with Coupled Processors: Computational Issues.	Queueing Syst.	2005	DBLP DOI BibTeX RDF	coupled processors, equilibrium distribution, tandem queue, boundary value problem
3	Aneesh Aggarwal, Manoj Franklin	Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	Clustered processor architecture, pipeline processors, interconnection architectures, load balancing and task assignment
3	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, George Xenoulis	Software-Based Self-Testing of Embedded Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor self-testing, Embedded processors, software-based self-testing, low-cost testing
3	Stephan Gatzka, Christian Hochberger	The AMIDAR Class of Reconfigurable Processors.	The Journal of Supercomputing	2005	DBLP DOI BibTeX RDF	processor architecture, adaptive computing, reconfigurable processors
3	Foto N. Afrati, Evripidis Bampis, Lucian Finta, Ioannis Milis	Scheduling trees with large communication delays on two identical processors.	J. Scheduling	2005	DBLP DOI BibTeX RDF	two processors, scheduling, trees, makespan, communication delays
3	Steve Leibson, James Kim	Configurable Processors: A New Era in Chip Design.	IEEE Computer	2005	DBLP DOI BibTeX RDF	nanometer silicon lithography, microprocessors, multiprocessor systems, MPSoCs, configurable processors
3	Marcelo de Souza Moraes, Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski	A constraint-based solution for on-line testing of processors embedded in real-time applications.	SBCCI	2005	DBLP DOI BibTeX RDF	test space exploration, real-time systems, embedded processors, on-line testing, software-based self-test
3	Steve Muir, Jonathan M. Smith	An operating system architecture for network processors.	ANCS	2005	DBLP DOI BibTeX RDF	operating systems, network processors
3	Arun Raghunath, Aaron R. Kunze, Erik J. Johnson, Vinod Balakrishnan	Framework for supporting multi-service edge packet processing on network processors.	ANCS	2005	DBLP DOI BibTeX RDF	edge packet processing, network processors, run-time adaptation
3	Byeong Kil Lee, Lizy Kurian John, Eugene John	Architectural Support for Accelerating Congestion Control Applications in Network Processors.	ASAP	2005	DBLP DOI BibTeX RDF
3	Nikolaos Kavvadias, Spiridon Nikolaidis	Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding.	ASAP	2005	DBLP DOI BibTeX RDF
3	Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia	Micro embedded monitoring for security in application specific instruction-set processors.	CASES	2005	DBLP DOI BibTeX RDF	micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring
3	Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis	Matrix register file and extended subwords: two techniques for embedded media processors.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	embedded media processors, multimedia kernels, sub-word parallelism, register file
3	Amirali Baniasadi	Balancing clustering-induced stalls to improve performance in clustered processors.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	clustering stalls, clustered processors
3	Soraya Ghiasi, Tom W. Keller, Freeman L. Rawson III	Scheduling for heterogeneous processors in server systems.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	scheduling, performance, power, heterogeneous processors