Search results for "random test generation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Irith Pomeranz, Sudhakar M. Reddy	Definition and application of approximate necessary assignments.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	necessary assignments, random test generation, test generation, stuck-at faults
2	Anna Moss	Constraint Patterns and Search Procedures for CP-Based Random Test Generation.	Haifa Verification Conference	2007	DBLP DOI BibTeX RDF
2	Carlos Pacheco, Shuvendu K. Lahiri, Michael D. Ernst, Thomas Ball	Feedback-Directed Random Test Generation.	ICSE	2007	DBLP DOI BibTeX RDF
2	Feng Shi, Yiorgos Makris	Fault simulation and random test generation for speed-independent circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	random test pattern generation, fault simulation, asynchronous circuits, speed-independent circuits
2	Christoph C. Michael, Gary McGraw, Michael Schatz, C. C. Walton	Genetic Algorithms for Dynamic Test Data Generation. (PDF / PS)	ASE	1997	DBLP DOI BibTeX RDF	program features, random test generation, genetic algorithms, genetic algorithms, software testing, combinatorial optimization, test generation, test data generation, test adequacy criteria
2	Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham	Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.	VTS	1996	DBLP DOI BibTeX RDF	waveform analysis, nonrobust tests, stuck-fault detection, signal waveform analysis, signal waveform integration, directed random test generation techniques, fault diagnosis, logic testing, redundancy, integrated circuit testing, combinational circuits, combinational circuits, automatic testing, detectability, fault coverage, test application time, redundant faults
2	Margot Karam, Gabriele Saucier	Functional versus random test generation for sequential circuits.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	simulation, Finite state machine, functional testing, graph traversal
2	Prathima Agrawal, Vishwani D. Agrawal	Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	probabilistic analysis of logic, random test generation, fault detection, detection probability, Combinational networks, path sensitizing
1	Arezoo Kamran, Mohammad Saeed Jahangiry, Zainalabedin Navabi	Merit based directed random test generation (MDRTG) scheme for combinational circuits.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi	Near optimal machine learning based random test generation.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Random Test Generation With Input Cube Avoidance.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Dynamic test compaction for a random test generation procedure with input cube avoidance.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Bhaskar Pal, Ansuman Banerjee, Arnab Sinha, Pallab Dasgupta	Accelerating Assertion Coverage With Adaptive Testbenches.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Bhaskar Pal, Arnab Sinha, Pallab Dasgupta, P. P. Chakrabarti, Kaushik De	Hardware accelerated constrained random test generation.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Deepak Mathaikutty, Sandeep K. Shukla, Sreekumar V. Kodakara, David J. Lilja, Ajit Dingankar	Design fault directed test generation for microprocessor validation.	DATE	2007	DBLP DOI BibTeX RDF
1	Carlos Pacheco, Michael D. Ernst	Randoop: feedback-directed random testing for Java.	OOPSLA Companion	2007	DBLP DOI BibTeX RDF	Java, random testing, automatic test generation
1	Hiren D. Patel, Sandeep K. Shukla	Model-driven Validation of SystemC Designs.	DAC	2007	DBLP DOI BibTeX RDF
1	Yukio Watanabe, Balazs Sallay, Brad W. Michael, Daniel A. Brokenshire, Gavin Meil, Hazim Shafi, Daisuke Hiraoka	An SPU reference model for simulation, random test generation and verification.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Ilya Wagner, Valeria Bertacco, Todd M. Austin	Depth-driven verification of simultaneous interfaces.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Alexander Krupp, Wolfgang Müller 0003	Classification trees for random tests and functional coverage.	DATE	2006	DBLP DOI BibTeX RDF
1	Evan Martin	Automated test generation for access control policies.	OOPSLA Companion	2006	DBLP DOI BibTeX RDF	test generation, XACML, access control policy
1	Kerstin Eder, Peter A. Flach, Hsiou-Wen Hsueh	Towards Automating Simulation-Based Design Verification Using ILP.	ILP	2006	DBLP DOI BibTeX RDF
1	Hao Shen, Yuzhuo Fu	Priority directed test generation for functional verification using neural networks.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Ilya Wagner, Valeria Bertacco, Todd M. Austin	StressTest: an automatic approach to test generation via activity monitors.	DAC	2005	DBLP DOI BibTeX RDF	directed-random simulation, architectural simulation, high-performance simulation
1	Prabhat Mishra, Nikil D. Dutt	Functional Coverage Driven Test Generation for Validation of Pipelined Processors.	DATE	2005	DBLP DOI BibTeX RDF
1	Zhonghai Wang, Yizheng Ye	The improvement for transaction level verification functional coverage.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Wushouer Silamu, Lin Kang	Design and Implementation of Distance Learning System based on .NET Component Technology.	ITCC	2003	DBLP DOI BibTeX RDF
1	Ponrudee Netisopakul, Lee J. White, John Morris	Data Coverage Testing.	APSEC	2002	DBLP DOI BibTeX RDF
1	Tom Chen, Andre Bai, Amjad Hajjar, Anneliese Amschler Andrews, Charles Anderson	Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	anti-random testing, code coverage improvement, test data generation
1	Hakim Kahlouche, César Viho, Massimo Zendri	Hardware Testing Using a Communication Protocol Conformance Testing Tool.	TACAS	1999	DBLP DOI BibTeX RDF
1	Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama, Tsuyoshi Takahashi, Ryuichi Satomura	Design Methodology of a 200MHz Superscalar Microprocessor: SH-4.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
1	Anneliese von Mayrhauser, Andre Bai, Tom Chen, Charles Anderson, Amjad Hajjar	Fast Antirandom (FAR) Test Generation. (PDF / PS)	HASE	1998	DBLP DOI BibTeX RDF	Antirandom test generation, generation efficiency, test coverage
1	Yervant Zorian, Hakim Bederr	An Effective Multi-Chip BIST Scheme.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	built-in self-test, DFT, MCM testing
1	Lee J. White	Regression Testing of GUI Event Interactions. (PDF / PS)	ICSM	1996	DBLP DOI BibTeX RDF	Pairwise Event Interaction, GUI Function Testing, Regression Testing, GUI Testing
1	Irith Pomeranz, Sudhakar M. Reddy	3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	David A. Wood, Garth A. Gibson, Randy H. Katz	Verifying a Multiprocessor Cache Controller Using Random Test Generation.	IEEE Design & Test of Computers	1990	DBLP DOI BibTeX RDF
1	Hussam Y. Abujbara, Sami A. Al-Arian	Self-testing and self-reconfiguration architecture for 2-D WSI arrays.	SPDP	1990	DBLP DOI BibTeX RDF
1	Debashis Bhattacharya, John P. Hayes	A hierarchical test generation methodology for digital circuits.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	high-level circuit models, test generation, fault modeling, digital circuits, hierarchical testing
1	Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli	PLATYPUS: a PLA test pattern generation tool.	DAC	1985	DBLP DOI BibTeX RDF
1	Prathima Agrawal, Vishwani D. Agrawal	On Monte Carlo Testing of Logic Tree Networks.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	Combinational tree networks, random test generation, logic testing, fault detection, detection probability
1	Donald M. Schuler, Ernst G. Ulrich, Thomas E. Baker, Susan P. Bryant	Random test generation using concurrent logic simulation.	DAC	1975	DBLP BibTeX RDF