Search results for "reconfigurable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Mounir Hamdi, J. Tong, C. W. Kin	Fast sorting algorithms on reconfigurable array of processors with optical buses. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm
5	Katherine Compton, Scott Hauck	Reconfigurable computing: a survey of systems and software.	ACM Comput. Surv.	2002	DBLP DOI BibTeX RDF	field-programmable, manual design, FPGA, reconfigurable computing, reconfigurable architectures, reconfigurable systems, Automatic design
5	Francisco Barat, Rudy Lauwereins	Reconfigurable Instruction Set Processors: A Survey. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	dynamically reconfigurable instruction set processor, reconfigurable functional unit, application specific instructions, reconfigurable computing
5	Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi	CODA-R: a reconfigurable testbed for real-time parallel computation.	RTCSA	1997	DBLP DOI BibTeX RDF	CODA-R, reconfigurable testbed, real-time parallel computation, reconfigurable field programmable gate arrays, total execution time, prototype reconfigurable real-time parallel system, real-time parallel architecture, field programmable gate arrays, real-time system, processing elements, computing engine
5	Saad AlKasabi, Salim Hariri	Performance analysis of a high-speed dynamically reconfigurable LAN. (PDF / PS)	LCN	1995	DBLP DOI BibTeX RDF	dynamically reconfigurable LAN, reconfigurable switch, highspeed multi-link ring local area network, switch reconfigurability, multi-link ring network, M/M/n, M/D/n, virtual channel occupancy probabilities, infinite state Markov model, finite state Markov model, OPNET tool, packet transfer time, virtual channel flow, performance evaluation, field programmable gate arrays, performance analysis, local area networks, reconfigurable architectures, wormhole routing, network performance, queuing systems, interconnection topologies, system throughput
4	Vikas Aggarwal, Alan D. George, Kishore Yalamanchili, Changil Yoon, Herman Lam, Greg Stitt	Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+.	SC-HPRCTA	2009	DBLP DOI BibTeX RDF	parallel programming, programming language, reconfigurable computing, productivity, portability, programming model
4	Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker	FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.	ARC	2009	DBLP DOI BibTeX RDF	design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools
4	Debora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin	The Need for Reconfigurable Routers in Networks-on-Chip.	ARC	2009	DBLP DOI BibTeX RDF	heterogeneous NoC, reconfigurable router, buffer, FIFO
4	Mahmood Fazlali, Mohammad K. Fallah, Mahdy Zolghadr, Ali Zakerolhosseini	A New Datapath Merging Method for Reconfigurable System.	ARC	2009	DBLP DOI BibTeX RDF	Datapath Merging, Maximum Weighted Clique Algorithm, High Level Synthesis, Reconfigurable Computing
4	José Manuel Moya, Javier Rodríguez, Julio Martín, Juan Carlos Vallejo, Pedro Malagón, Álvaro Araujo, Juan-Mariano de Goyeneche, Agustín Rubio, Elena Romero, Daniel Villanueva, Octavio Nieto-Taladriz, Carlos A. López-Barrio	SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems.	ARC	2009	DBLP DOI BibTeX RDF	Application-transparent adaptation, Ubiquitous computing, Reconfigurable hardware, Adaptable architectures
4	Chenxin Zhang, Thomas Lenart, Henrik Svensson, Viktor Öwall	Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications.	ReConFig	2009	DBLP DOI BibTeX RDF	Dynamically reconfigurable cell array, Hybrid interconnect, FFT, Coarse-grained reconfigurable architecture
4	Laïd Kahloul, Allaoua Chaoui	Code mobility modeling: a temporal labeled reconfigurable nets.	MOBILWARE	2008	DBLP DOI BibTeX RDF	formal tools, labeled reconfigurable nets, temporal labeled reconfigurable nets, code mobility, design paradigms
4	Adriano Idalgo, Nahri Moreano	DNA Physical Mapping on a Reconfigurable Platform.	ARC	2008	DBLP DOI BibTeX RDF	Consecutive ones problem, Software/hardware partitioning, Reconfigurable architectures
4	Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis	Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture.	The Journal of Supercomputing	2007	DBLP DOI BibTeX RDF	Coarse-grained reconfigurable arrays, Data bandwidth bottleneck, Reconfigurable computing, Data reuse, Compiler techniques
4	Kang Sun, Jun Zheng, Yuanyuan Li, Xuezeng Pan	Design of a Simulator for Mesh-Based Reconfigurable Architectures.	NPC	2007	DBLP DOI BibTeX RDF	simulator, reconfigurable computing, dynamic reconfiguration, reconfigurable mesh
4	Peiheng Zhang, Guangming Tan, Guang R. Gao	Implementation of the Smith-Waterman algorithm on a reconfigurable supercomputing platform.	HPRCTA	2007	DBLP DOI BibTeX RDF	reconfigurable supercomputing, FPGA, coprocessor, Smith-Waterman algorithm
4	Esam El-Araby, Ivan Gonzalez, Tarek A. El-Ghazawi	Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing.	HPRCTA	2007	DBLP DOI BibTeX RDF	field programmable gate arrays (FPGA), high performance computing, reconfigurable computing, dynamic partial reconfiguration
4	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration for coarse grained reconfigurable arrays.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	coarse-grained reconfigurable arrays, reconfigurable computing, modulo scheduling, architectural exploration
4	Grigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis	A unified evaluation framework for coarse grained reconfigurable array architectures.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	coarse-grained reconfigurable arrays, reconfigurable romputing, Modulo scheduling, architectural exploration
4	Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab	Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches.	ASP-DAC	2007	DBLP DOI BibTeX RDF	reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current
4	Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein	Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Term Rewriting Systems (TRS), algebraic manipulation, dynamically reconfigurable systems, Fast Fourier Transform (FFT), reconfigurable computing, systolic arrays, rewriting-logic
4	Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis	Partitioning Methodology for Heterogeneous Reconfigurable Functional Units.	The Journal of Supercomputing	2006	DBLP DOI BibTeX RDF	heterogeneous reconfigurable architectures, coarse-grain reconfigurable hardware, scheduling, FPGA, partitioning, performance improvements
4	Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems.	ARC	2006	DBLP DOI BibTeX RDF	RSA, Elliptic Curve Cryptography (ECC), Public-Key Cryptography (PKC), Reconfigurable architecture, FPGA implementation
4	Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen	Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	heterogeneous reconfigurable multimedia systems, energy efficiency, reconfigurable computing, discrete wavelet transform, lifting scheme
4	Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo	The design of dynamically reconfigurable datapath coprocessors.	ACM Trans. Embedded Comput. Syst.	2004	DBLP DOI BibTeX RDF	coarse-grain reconfigurable fabric, reconfigurable datapath, Loop pipelining, interconnection design, datapath synthesis
4	Sakir Sezer, Ciaran Toal, Emi Garcia, V. Stewart	A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling.	IPDPS	2004	DBLP DOI BibTeX RDF	reconfigurable packet scheduling, SCFQ, Reconfigurable architectures, WFQ, network processing
4	Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan	Reconfigurable platforms for ubiquitous computing.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	ubiquitous computing, communication, networks-on-chip, reconfiguration, reconfigurable hardware, dynamic power management, reconfigurable processors
4	Francisco Barat, Rudy Lauwereins, Geert Deconinck	Reconfigurable Instruction Set Processors from a Hardware/Software Perspective.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	Reconfigurable instruction set processor overview, compiler, microprocessor, reconfigurable logic
4	Ali Akoglu, Aravind Dasu, Arvind Sudarsanam, Mayur Srinivasan, Sethuraman Panchanathan	Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	reconfigurable media processor, recurring pattern analyzer, mobile multimedia processing, partition, dynamic reconfiguration, reconfigurable architectures, data flow graph, control flow graph, MPEG4, hardware software co-design, hardware software partitioning, routing architecture
4	David R. Martinez, Tyler J. Moeller, Ken Teitelbaum	Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	VLSI rader signal processor, front end high performance filtering, digital filtering mapped to reconfigurable computing, commercial FPGA hardware, reconfigurable hardware
4	Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, Eliseu M. Chaves Filho	MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	reconfigurable cell array, bit-correlation, dynamic reconfiguration, Single Instruction Multiple Data, multimedia applications, video compression, MPEG-2, Reconfigurable systems, data encryption, target recognition
4	Akihiro Matsuura, Akira Nagoya	Summation Algorithms on Constrained Reconfigurable Meshes.	ISPAN	1999	DBLP DOI BibTeX RDF	constrained reconfigurable mesh, Bit summation, parallel algorithm, reconfigurable mesh
4	Koji Nakano, Stephan Olariu	An Efficient Algorithm for Row Minima Computations on Basic Reconfigurable Meshes.	IEEE Trans. Parallel Distrib. Syst.	1998	DBLP DOI BibTeX RDF	Monotone matrices, totally monotone matrices, row minima, basic reconfigurable meshes, cellular system design, VLSI design, search problems, reconfigurable meshes, facility location problems
4	Suchendra M. Bhandarkar, Hamid R. Arabnia	Parallel Computer Vision on a Reconfigurable Multiprocessor Network.	IEEE Trans. Parallel Distrib. Syst.	1997	DBLP DOI BibTeX RDF	Reconfigurable multiring network, computer vision, parallel algorithms, image processing, parallel processing, distributed algorithms, distributed processing, reconfigurable architectures, scalable architectures
4	Itsuo Takanami, Tadayoshi Horita	A built-in self-reconfigurable scheme for 3D mesh arrays.	ISPAN	1997	DBLP DOI BibTeX RDF	fault tolerant 3D processor arrays, 3D mesh arrays, self-reconfigurable scheme, track switches, fault compensation, reconfiguration, reconfigurable architectures
4	Steven M. P. Yip, Nicholas Bambos	Scalable routing schemes for massively parallel processing using reconfigurable optical interconnect. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	scalable routing schemes, reconfigurable optical interconnect, message broadcasting, massively parallel processing system, randomly generated packets, device capabilities, parallel processing, reconfigurable architectures, optical interconnections, message routing, massively parallel processing
4	Mounir Hamdi, Yi Pan	Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses.	ISPAN	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations
4	Patrick W. Dowd, James A. Perreault, John C. Chu, D. C. Hoffmeister, D. Crouse	LIGHTNING: A Scalable Dynamically Reconfigurable Hierarchical WDM Network for High-Performance Clustering. (PDF / PS)	HPDC	1995	DBLP DOI BibTeX RDF	scalable dynamically reconfigurable hierarchical WDM network, high-performance clustering, supercomputer interconnection, optical network testbed, distributed shared memory environment, single-hop all-optical communication, n-level hierarchy, highly fault tolerant system behavior, memory interface, optical devices, scalability, parallel processing, reconfigurable architectures, system architecture, wavelength division multiplexing, wavelength division multiplexing, optical interconnections, optical information processing, LIGHTNING, traffic intensities
4	Nikolaos Gaitanis, Panagiotis Kostarakis, Antonis M. Paschalis	Totally Self Checking reconfigurable duplication system with separate internal fault indication.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	decision circuits, totally self checking system, reconfigurable duplication system, separate internal fault indication, single cell fault model, functional self checking units, decision circuit, indication outputs, nonstop repair, fault diagnosis, logic testing, built-in self test, redundancy, redundancy, reconfigurable architectures, switching circuits, error indication
4	Hossam A. ElGindy, Lachlan Wetherall	A simple Voronoi diagram algorithm for a reconfigurable mesh. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	Voronoi diagram algorithm, planar points, worst case running, communication diameter, scheduling, load balancing, computational geometry, reconfigurable architectures, reconfigurable mesh
4	Lizy Kurian John, Daniel Brewer, Eugene John	Design of a highly reconfigurable interconnect for array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies
4	Hussein M. Alnuweiri	Constant-Time Parallel Algorithms for Image Labeling on a Reconfigurable Network of Processors.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	constant-time parallel algorithms, reconfigurable network of processors, minimum-labeled PE, timecomplexity, parallel algorithms, computational complexity, image recognition, reconfigurable architectures, multiprocessorinterconnection networks, image labeling
3	Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Michael Ullmann, Klaus D. Müller-Glaser, Jürgen Becker	Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Josef Angermeier, Christophe Bobda, Mateusz Majer, Jürgen Teich	Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Heiko Hinkelmann, Peter Zipf, Manfred Glesner	Dynamically Reconfigurable Systems for Wireless Sensor Networks.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Roland Kasper, Steffen Toscher	Reconfigurable Controllers - A Mechatronic Systems Approach.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Enno Lübbers, Marco Platzner	ReconOS: An Operating System for Dynamically Reconfigurable Hardware.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Christian Haubelt, Dirk Koch, Felix Reimann, Thilo Streichert, Jürgen Teich	ReCoNets - Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen	ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Alexander Thomas, Jürgen Becker	Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Tobias G. Noll, Thorsten von Sydow, Bernd Neumann, Jochen Schleifer, Thomas Coenen, Götz Kappen	Reconfigurable Components for Application-Specific Processor Architectures.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Marc Stöttinger, Felix Madlener, Sorin A. Huss	Procedures for Securing ECC Implementations Against Differential Power Analysis Using Reconfigurable Architectures.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel	Evaluation and Design Methods for Processor-Like Reconfigurable Architectures.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Andreas Schallenberg, Wolfgang Nebel, Andreas Herrholz, Philipp A. Hartmann, Kim Grüttner, Frank Oppenheimer	PolyDyn - Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf	FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Christopher Claus, Walter Stechele	AutoVision - Reconfigurable Hardware Acceleration for Video-Based Driver Assistance.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Carsten Albrecht, Jürgen Foag, Roman Koch, Erik Maehle, Thilo Pionteck	DynaCORE - Dynamically Reconfigurable Coprocessor for Network Processors.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Matthias Alles, Timo Vogt, Christian Brehm, Norbert Wehn	FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
3	Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum	Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.	ISLPED	2010	DBLP DOI BibTeX RDF	computer aided design, placement, dynamic reconfiguration, temperature, reconfigurable systems
3	Vincenzo Rana, Donatella Sciuto	A novel design framework for the design of reconfigurable systems based on NoCs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	network-on-chip, reconfigurable computing, design flow, mapping algorithm
3	Neil Gershenfeld, David Dalrymple, Kailiang Chen, Ara Knaian, Forrest Green, Erik D. Demaine, Scott Greenwald, Peter Schmidt-Nielsen	Reconfigurable asynchronous logic automata: (RALA).	POPL	2010	DBLP DOI BibTeX RDF	reconfigurable, logic, asynchronous, automata
3	Sansiri Tanachutiwat, Ji Ung Lee, Wei Wang 0003, Chun Yung Sung	Reconfigurable multi-function logic based on graphene P-N junctions.	DAC	2010	DBLP DOI BibTeX RDF	graphene, p-n junction, logic gate, device, reconfigurable logic
3	Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol	An efficient dynamically reconfigurable on-chip network architecture.	DAC	2010	DBLP DOI BibTeX RDF	performance, reconfigurable, topology, power, NoC
3	Ananth Nallamuthu, Melissa C. Smith, Scott S. Hampton, Pratul K. Agarwal, Sadaf R. Alam	Energy efficient biomolecular simulations with FPGA-based reconfigurable computing.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	biomolecular simulations, lammps, fpga, reconfigurable computing, molecular dynamics
3	Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen	Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (gals), low-power and high-performance design, reconfigurable fifos, voltage/frequency islands (vfis), networks-on-chip (nocs)
3	Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker	A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design
3	Kristian Stevens, Henry Chen, Terry Filiba, Peter McMahon, Yun S. Song	Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	genome resequencing, fpga, acceleration, reconfigurable logic
3	Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev	A 3d-audio reconfigurable processor.	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable computing, communication systems, beamforming, 3d-audio, wave field synthesis
3	Mingjie Lin, Ilia A. Lebedev, John Wawrzynek	High-throughput bayesian computing machine with reconfigurable hardware.	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable hardware, bayesian computing
3	Zhimin Chen, Richard Neil Pittman, Alessandro Forin	Combining multicore and reconfigurable instruction set extensions.	FPGA	2010	DBLP DOI BibTeX RDF	extensible microprocessors, reconfigurable instruction set extensions, embedded, multi-core
3	Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin	Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration
3	ByungHyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim	Thermal sensor allocation and placement for reconfigurable systems.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	optimal placement, unate-covering problem, reconfigurable system, Thermal sensor
3	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays.	The Journal of Supercomputing	2009	DBLP DOI BibTeX RDF	Coarse-grained reconfigurable arrays, High productivity tools, Modulo scheduling, Architectural exploration, Compiler techniques
3	Yong Dou, Guiming Wu, Jinhui Xu, Xingming Zhou	A coarse-grained reconfigurable computing architecture with loop self-pipelining.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	reconfigurable computing, data driven, loop pipelining, register promotion
3	Minghui Wang, Shugen Ma, Bin Li, Yuechao Wang	Configuration representation and reconfiguration optimization for the reconfigurable robots with independent manipulation.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	reconfigurable robots with independent manipulation, configuration representation, reconfiguration optimization
3	Esam El-Araby, Ivan Gonzalez, Tarek A. El-Ghazawi	Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing.	TRETS	2009	DBLP DOI BibTeX RDF	field programmable gate arrays (FPGA), High performance computing, reconfigurable computing, dynamic partial reconfiguration
3	Kazuteru Namba, Yoshikazu Matsui, Hideo Ito	Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding.	J. Electronic Testing	2009	DBLP DOI BibTeX RDF	IP core testing, Fixing-flipping coding, Fixing-shifting-flipping coding, Test compression, Reconfigurable network
3	Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor N. Mudge	Reconfigurable Multicore Server Processors for Low Power Operation.	SAMOS	2009	DBLP DOI BibTeX RDF	Server Architectures, Low Power, Reconfigurable
3	Walid A. Najjar, Jason R. Villarreal	Reconfigurable Computing in the New Age of Parallelism.	SAMOS	2009	DBLP DOI BibTeX RDF	FPGAs, Reconfigurable computing
3	Gongyu Wang, Greg Stitt, Herman Lam, Alan D. George	A framework for core-level modeling and design of reconfigurable computing algorithms.	SC-HPRCTA	2009	DBLP DOI BibTeX RDF
3	Vikas Aggarwal, Rafael Garcia, Greg Stitt, Alan D. George, Herman Lam	SCF: a device- and language-independent task coordination framework for reconfigurable, heterogeneous systems.	SC-HPRCTA	2009	DBLP DOI BibTeX RDF	communication, coordination, reconfigurable computing, productivity, portability, heterogeneous computing, accelerators
3	Yupeng Chen, Bertil Schmidt, Douglas L. Maskell	A Reconfigurable Bloom Filter Architecture for BLASTN.	ARCS	2009	DBLP DOI BibTeX RDF	genomic sequence analysis, bioinformatics, reconfigurable computing, Bloom filter
3	Björn Osterloh, Harald Michalik, Björn Fiethe	SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs.	ARCS	2009	DBLP DOI BibTeX RDF	SoCWire, dynamic reconfigurable system, Sytem-on-Chip, Network-on-Chip, SRAM-based FPGA, VMC
3	Viviane Lucy Santos de Souza, Victor Wanderley Costa de Medeiros, Manoel Eusebio de Lima	Architecture for dense matrix multiplication on a high-performance reconfigurable system.	SBCCI	2009	DBLP DOI BibTeX RDF	BRAMs (RAM blocks), MAC (multiplier unit), RASC (reconfigurable application-specific computing), performance, FPGA (field programmable gate array), parallelism, matrix multiplication, data reuse
3	Juan Fernando Eusse Giraldo, Michael Hübner, Ricardo Pezzuol Jacobi	BRICK: a multi-context expression grained reconfigurable architecture.	SBCCI	2009	DBLP DOI BibTeX RDF	validation, reconfigurable computing, MIMO, SystemC, co-simulation, coarse grain
3	Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz	Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.	SBCCI	2009	DBLP DOI BibTeX RDF	reconfigurable router, fault tolerance, reliability, network-on-chip, NoC
3	Jie Li, Haibo He, Hong Man, Sachi Desai	A General-Purpose FPGA-Based Reconfigurable Platform for Video and Image Processing.	ISNN	2009	DBLP DOI BibTeX RDF	video and image processing, edge detection, Reconfigurable system, FPGA design, image scaling
3	Yanxia Shen, Tai Li, Zhicheng Ji	Research on the Reconfigurable Implementation of Neural Network Controller Based on FPGA for DC-DC Converters.	ISNN	2009	DBLP DOI BibTeX RDF	Reconfigurable design, Neural network, Hardware implementation, FPGA implementation
3	Jonathan Hook, Stuart Taylor, Alex Butler, Nicolas Villar, Shahram Izadi	A reconfigurable ferromagnetic input device.	UIST	2009	DBLP DOI BibTeX RDF	ferromagnetic sensing, malleable surface, reconfigurable input device, tangibles, multi-touch
3	Yoonjin Kim, Rabi N. Mahapatra	Dynamic context management for low power coarse-grained reconfigurable architecture.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	context word, embedded systems, system-on-chip (soc), digital signal processing, coarse-grained reconfigurable architecture, configuration cache
3	Yiqing Huang, Qin Liu, Satoshi Goto, Takeshi Ikenaga	Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reconfigurable architecture, h.264, vlsi
3	Shinya Kubota, Minoru Watanabe	A nine-context programmable optically reconfigurable gate array with semiconductor lasers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	holographic memory, optically reconfigurable gate arrays, field programmable gate arrays
3	Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux	On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch
3	Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja	A reconfigurable stochastic architecture for highly reliable computing.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	stochastic logic, reconfigurable architecture, reliable computing
3	Yoonjin Kim, Rabi N. Mahapatra	Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems.	DAC	2009	DBLP DOI BibTeX RDF	coarse-grained reconfigurable architecture (CGRA), computing hierarchy, embedded systems
3	Zhiguo Ge, Tulika Mitra, Weng-Fai Wong	A DVS-based pipelined reconfigurable instruction memory.	DAC	2009	DBLP DOI BibTeX RDF	reconfigurable memory, low power, instruction cache
3	Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin	Automatic bus macro placement for partially reconfigurable FPGA designs.	FPGA	2009	DBLP DOI BibTeX RDF	emips, reconfigurable computing, dynamic partial reconfiguration, floor-planning
3	Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu	HMMer acceleration using systolic array based reconfigurable architecture.	FPGA	2009	DBLP DOI BibTeX RDF	reconfigurable., systolic array, acceleration, hmmer
3	Like Yan, Gang Wang, Tianzhou Chen	The input-aware dynamic adaptation of area and performance for reconfigurable accelerator.	FPGA	2009	DBLP DOI BibTeX RDF	dynamic adaption, reconfigurable system, loop unrolling, loop accelerator
3	Jason Cong, Karthik Gururaj, Guoling Han	Synthesis of reconfigurable high-performance multicore systems.	FPGA	2009	DBLP DOI BibTeX RDF	coprocessor synthesis, reconfigurable high-performance computing, design space exploration