Search results for "reconfigurable architectures"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Taewook Oh, Bernhard Egger, Hyunchul Park, Scott A. Mahlke	Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures.	LCTES	2009	DBLP DOI BibTeX RDF	software pipelining, placement and routing, coarse-grained reconfigurable architectures
3	Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas	06141 Abstracts Collection -- Dynamically Reconfigurable Architectures.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
3	Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas	06141 Executive Summary -- Dynamically Reconfigurable Architectures.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
3	Rainer Buchty	Reconfigurable Architectures and Instruction Sets: Programmability, Code Generation, and Program Execution.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
3	Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh	Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	multimedia, computer graphics, reconfigurable architectures, SIMD, hierarchical trees
2	Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen	Benchmarking Reconfigurable Architectures in the Mobile Domain.	FCCM	2009	DBLP DOI BibTeX RDF	Mobile Domain, FPGA, Low Power, Reconfigurable Architectures
2	Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan	Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures.	ARC	2009	DBLP DOI BibTeX RDF
2	Sebastian Lange, Martin Middendorf	Design Aspects of Multi-level Reconfigurable Architectures.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	multi-level reconfiguration, dynamic reconfiguration, reconfigurable architecture
2	Ozana Silvia Dragomir, Todor Stefanov, Koen Bertels	Loop unrolling and shifting for reconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
2	Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa	Towards benchmarking energy efficiency of reconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
2	Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker	Fine grain reconfigurable architectures.	FPL	2008	DBLP DOI BibTeX RDF
2	Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi	Shared reconfigurable architectures for CMPS.	FPL	2008	DBLP DOI BibTeX RDF
2	Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich	Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures.	PATMOS	2008	DBLP DOI BibTeX RDF
2	Hyunchul Park, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-seok Kim	Edge-centric modulo scheduling for coarse-grained reconfigurable architectures.	PACT	2008	DBLP DOI BibTeX RDF	operand routing, programmable accelerator, software pipelining, coarse-grained reconfigurable architecture
2	Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi	Compiling custom instructions onto expression-grained reconfigurable architectures.	CASES	2008	DBLP DOI BibTeX RDF	horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures
2	Carlo Curino, Luca Fossati, Vincenzo Rana, Francesco Redaelli, Marco D. Santambrogio, Donatella Sciuto	The Shining embedded system design methodology based on self dynamic reconfigurable architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek	SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Adriano Idalgo, Nahri Moreano	DNA Physical Mapping on a Reconfigurable Platform.	ARC	2008	DBLP DOI BibTeX RDF	Consecutive ones problem, Software/hardware partitioning, Reconfigurable architectures
2	Kang Sun, Jun Zheng, Yuanyuan Li, Xuezeng Pan	Design of a Simulator for Mesh-Based Reconfigurable Architectures.	NPC	2007	DBLP DOI BibTeX RDF	simulator, reconfigurable computing, dynamic reconfiguration, reconfigurable mesh
2	Ricardo S. Ferreira, Alisson Garcia, Tiago Teixeira, João M. P. Cardoso	A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Ulrich Ramacher	Software-Defined Radio Prospects for Multistandard Mobile Phones.	IEEE Computer	2007	DBLP DOI BibTeX RDF	mobile phone standard, software-defined radio technologies, MuSIC-1 chip, SDR baseband processors, reconfigurable architectures, embedded computing
2	Sajid Baloch, Tughrul Arslan, Adrian Stoica	An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures.	FPL	2006	DBLP DOI BibTeX RDF
2	Tobias Oppold	Evaluation and Design of Processor-Like Reconfigurable Architectures.	FPL	2006	DBLP DOI BibTeX RDF
2	Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh	Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures.	FPL	2006	DBLP DOI BibTeX RDF
2	Daniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón, Rudi H. van Els, Renato P. Almeida	Implementation of dispatching algorithms for elevator systems using reconfigurable architectures.	SBCCI	2006	DBLP DOI BibTeX RDF	elevator group control system, field programmable gate arrays
2	Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Sebastian Lange, Martin Middendorf	Multi-level reconfigurable architectures in the switch model.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich (eds.)	Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Hyunchul Park, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke	Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures.	CASES	2006	DBLP DOI BibTeX RDF	graph embedding, modulo scheduling, coarse-grained reconfigurable architecture
2	Leipo Yan, Thambipillai Srikanthan, Niu Gang	Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures.	LCTES	2006	DBLP DOI BibTeX RDF	CGRA, VLIW, hardware/software partitioning, delay estimation, area estimation
2	Douglas L. Maskell, Timothy F. Oliver	Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Klaus Waldschmidt, Jan Haase, Andreas Hofmann, Markus Damm, Dennis Hauser	Reliability-Aware Power Management Of Multi-Core Systems (MPSoCs).	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Andreas Herkersdorf, Christopher Claus, Michael Meitinger, Rainer Ohlendorf, Thomas Wild	Reconfigurable Processing Units vs. Reconfigurable Interconnects.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal, Paul M. Heysters	Efficient architectures for streaming applications.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Norbert Wehn, Timo Vogt, Christian Neeb	A Reconfigurable Outer Modem Platform for Future Communications Systems.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	József Vásárhelyi, Péter Serfözö	Analysis of Mojette Transform Implementation on Reconfigurable Hardware.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Jürgen Becker, Michael Hübner, Katarina Paulsson	Physical 2D Morphware and Power Reduction Methods for Everyone.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Peter M. Athanas	The (empty?) Promise of FPGA Supercomputing.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Sunil Shukla, Neil W. Bergmann, Jürgen Becker	QUKU: A Coarse Grained Paradigm for FPGAs.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Walter Stechele	Dynamically Reconfigurable Systems-on-Chip.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Florian Dittmann	Reconfiguration Time Aware Processing on FPGAs.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Oliver Diessel, Shannon Koh	Enabling RTR for industry.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Diana Göhringer, Mateusz Majer, Jürgen Teich	Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Sven Heithecker, Amilcar do Carmo Lucas, Rolf Ernst	FlexFilm - an Image Processor for Digital Film Processing.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	David A. Kearney, Mark Jasiunas	Managing power amongst a group of networked embedded fpgas using dynamic reconfiguration and task migration.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Peter Zipf, Manfred Glesner	Towards an Automated Design of Application-specific Reconfigurable Logic.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
2	Georgi Gaydadjiev, Stamatis Vassiliadis	SAD Prefetching for MPEG4 Using Flux Caches.	SAMOS	2006	DBLP DOI BibTeX RDF	Flux caches, Prefetching mechanisms, Multimedia, Reconfigurable architectures
2	Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood	Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures.	International Journal of Parallel Programming	2005	DBLP DOI BibTeX RDF	cycle-accurate hardware profiling, performance, architecture, Reconfigurable
2	Fredy Rivera, Milagros Fernández, Nader Bagherzadeh	An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures.	DSD	2005	DBLP DOI BibTeX RDF
2	Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis	A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Markus Koester, Mario Porrmann, Ulrich Rückert	Placement-Oriented Modeling of Partially Reconfigurable Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Lilian Bossuet, Guy Gogniat, Jean Luc Philippe	Generic Design Space Exploration for Reconfigurable Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon	Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh	Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
2	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt	Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration.	DAC	2005	DBLP DOI BibTeX RDF	HW-SW partitioning, linear placement, partial dynamic reconfiguration
2	Chris Sullivan, Alex Wilson, Stephen Chappell	Deterministic Hardware Synthesis for Compiling High-Level Descriptions to Heterogeneous Reconfigurable Architectures.	HICSS	2005	DBLP DOI BibTeX RDF
2	Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon	Dynamic hardware multiplexing for coarse grain reconfigurable architectures.	FPGA	2005	DBLP DOI BibTeX RDF
2	Juanjo Noguera, Rosa M. Badia	Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling.	ACM Trans. Embedded Comput. Syst.	2004	DBLP DOI BibTeX RDF	Adaptable architectures and microarchitectures, runtime support for dynamic reconfiguration, dynamic scheduling
2	Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. Gupta	Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures.	FPL	2004	DBLP DOI BibTeX RDF
2	Nikhil Bansal, Sumit Gupta, Nikil Dutt, Alexandru Nicolau, Rajesh Gupta	Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures.	DATE	2004	DBLP DOI BibTeX RDF
2	Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis	Loading rho-µ-Code: Design Considerations.	SAMOS	2004	DBLP DOI BibTeX RDF	MOLEN, loading microcode, implementation, Reconfigurable architectures
2	Seonil Choi, Ju-wook Jang, Sumit Mohanty, Viktor K. Prasanna	Domain-Specific Modeling for Rapid Energy Estimation of Reconfigurable Architectures.	The Journal of Supercomputing	2003	DBLP DOI BibTeX RDF	FPGA, energy optimization, domain-specific modeling, energy estimation
2	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Compilation Approach for Coarse-Grained Reconfigurable Architectures.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
2	Lilian Bossuet, Guy Gogniat, Jean Luc Philippe	Communication Costs Driven Design Space Exploration for Reconfigurable Architectures.	FPL	2003	DBLP DOI BibTeX RDF
2	Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon	Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability.	IPDPS	2003	DBLP DOI BibTeX RDF
2	Juanjo Noguera, Rosa M. Badia	System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures.	CASES	2003	DBLP DOI BibTeX RDF	reconfigurable computing, dynamic scheduling, clock-gating, frequency scaling, power-performance trade-offs
2	Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins	Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling.	DATE	2003	DBLP DOI BibTeX RDF
2	Marcos Sanchez-Elez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida	Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures.	DATE	2003	DBLP DOI BibTeX RDF
2	Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet	Fast prototyping of reconfigurable architectures from a C program.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	An algorithm for mapping loops onto coarse-grained reconfigurable architectures.	LCTES	2003	DBLP DOI BibTeX RDF	ALU array, memory bandwidth utilization, coarse-grained reconfigurable architecture, mapping algorithm
2	Juanjo Noguera, Rosa M. Badia	HW/SW codesign techniques for dynamically reconfigurable architectures.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
2	Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida	A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model.	FPL	2002	DBLP DOI BibTeX RDF
2	Marcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Román Hermida, Nader Bagherzadeh, Fadi J. Kurdahi	A Complete Data Scheduler for Multi-Context Reconfigurable Architectures.	DATE	2002	DBLP DOI BibTeX RDF
2	Juanjo Noguera, Rosa M. Badia	Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures.	CODES	2002	DBLP DOI BibTeX RDF	dynamic run-time scheduling, reconfigurable architectures
2	Rafael Maestre, F. Kurdahl, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh	A formal approach to context scheduling for multicontext reconfigurable architectures.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Alan A. Bertossi, Alessandro Mei	Optimal Segmented Scan and Simulation of Reconfigurable Architectures on Fixed Connection Networks.	HiPC	2000	DBLP DOI BibTeX RDF
2	Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger	Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures.	FPL	2000	DBLP DOI BibTeX RDF
2	Yanbing Li, Tim Callahan, Ervan Darnell, Randolph E. Harr, Uday Kurkure, Jon Stockwood	Hardware-software co-design of embedded reconfigurable architectures.	DAC	2000	DBLP DOI BibTeX RDF
2	Steven K. Sinha, Peter Kamarchik, Seth Copen Goldstein	Tunable Fault Tolerance for Runtime Reconfigurable Architectures.	FCCM	2000	DBLP DOI BibTeX RDF
2	Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh	Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures.	FCCM	2000	DBLP DOI BibTeX RDF
2	Juanjo Noguera, Rosa M. Badia	Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures.	ISSS	2000	DBLP DOI BibTeX RDF
2	Srihari Cadambi, Seth Copen Goldstein	Efficient Place and Route for Pipeline Reconfigurable Architectures. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
2	Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh	Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
2	Kiran Bondalapati, Viktor K. Prasanna	Dynamic Precision Management for Loop Computations on Reconfigurable Architectures.	FCCM	1999	DBLP DOI BibTeX RDF	Reconfigurable Computing, Precision, Loops
2	Edwige Pissaloux	On Parallel Reconfigurable Architectures for Image Processing.	ACPC	1999	DBLP DOI BibTeX RDF
2	Kiran Bondalapati, Viktor K. Prasanna	Mapping Loops onto Reconfigurable Architectures.	FPL	1998	DBLP DOI BibTeX RDF
2	Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri	An Effective Design System for Dynamically Reconfigurable Architectures.	FCCM	1998	DBLP DOI BibTeX RDF
1	Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich	Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	Zain-ul-Abdin, Bertil Svensson	Occam-pi for Programming of Massively Parallel Reconfigurable Architectures.	Int. J. Reconfig. Comp.	2012	DBLP DOI BibTeX RDF
1	André Seffrin, Sorin A. Huss	Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
1	Artjom Grudnitsky, Lars Bauer, Jörg Henkel	Partial online-synthesis for mixed-grained reconfigurable architectures.	DATE	2012	DBLP BibTeX RDF
1	Giovanni Mariani, Vlad Mihai Sima, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, Koen Bertels	Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures.	DATE	2012	DBLP BibTeX RDF
1	Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunheung Paek	Memory access optimization in compilation for coarse-grained reconfigurable architectures.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Rani Gnanaolivu, Theodore S. Norvell, Ramachandran Venkatesan	Analysis of Inner-Loop Mapping onto Coarse-Grained Reconfigurable Architectures Using Hybrid Particle Swarm Optimization.	IJOCI	2011	DBLP DOI BibTeX RDF
1	Arnaud Lanoix, Julien Dormoy, Olga Kouchnarenko	Combining Proof and Model-checking to Validate Reconfigurable Architectures.	Electr. Notes Theor. Comput. Sci.	2011	DBLP DOI BibTeX RDF
1	Ganghee Lee, Kiyoung Choi, Nikil D. Dutt	Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Doosan Cho, Yunheung Paek	High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Ismail Ktata, Ghaffari Fakhreddine, Bertrand Granado, Mohamed Abid	Dynamic Application Model for Scheduling with Uncertainty on Reconfigurable Architectures.	Int. J. Reconfig. Comp.	2011	DBLP DOI BibTeX RDF
1	Aravind Dasu, João M. P. Cardoso, Eli Bozorgzadeh, Jürgen Becker	Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010).	Int. J. Reconfig. Comp.	2011	DBLP DOI BibTeX RDF
1	Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures.	FPL	2011	DBLP DOI BibTeX RDF