Search results for "register renaming"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Masaharu Goto, Toshinori Sato	Leakage Energy Reduction in Register Renaming.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF	super-scalar processors, embedded processors, register renaming, deep submicron, Leakage energy
3	Hazem I. Shehata, Mark Aagaard	A general decomposition strategy for verifying register renaming.	DAC	2004	DBLP DOI BibTeX RDF	formal design verification, register renaming, pipelined circuits
3	Nicola Zingirian, Massimo Maresca	Selective Register Renaming: A Compiler-Driven Approach to Dynamic Register Renaming.	HPCN	2001	DBLP DOI BibTeX RDF	Dynamic Register Renaming, Instruction Level Parallelism, Register Allocation, Loop Parallelization
3	Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung	Register renaming for x86 superscalar design. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	Intel x86 superscalar design, storage conflicts, data lengths, register write, register read, hardware renaming schemes, aggressive superscalar machine model, parallel architectures, instruction level parallelism, simulation results, microprocessor chips, register renaming
2	Hui Zeng, Ju-Young Jung, Kanad Ghose, Dmitry Ponomarev	Energy-efficient renaming with register versioning.	ISLPED	2009	DBLP DOI BibTeX RDF	microprocessor, register renaming
2	Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang, Huimin Cui, Dongrui Fan	Optimized Register Renaming Scheme for Stack-Based x86 Operations.	ARCS	2007	DBLP DOI BibTeX RDF
2	Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose	Energy Efficient Register Renaming.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Dezsö Sima	The Design Space of Register Renaming Techniques.	IEEE Micro	2000	DBLP DOI BibTeX RDF
2	Nicola Zingirian, Massimo Maresca	Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures.	CAMP	2000	DBLP DOI BibTeX RDF	loop regularization, instruction level parallel architectures, instruction reordering, image processing, embedded systems, embedded systems, video processing, digital signal processors, register renaming
2	Nicola Zingirian, Massimo Maresca	Run-Time Support to Register Allocation for Loop Parallelization of Image Processing Programs.	HPCN	2000	DBLP DOI BibTeX RDF	Dynamic Register Renaming, Image Processing, Instruction Level Parallelism, Register Allocation, Loop Parallelization
2	Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin	The Design of a Register Renaming Unit.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
2	Roger Espasa, Mateo Valero, James E. Smith	Out-of-Order Vector Architectures.	MICRO	1997	DBLP BibTeX RDF	memory traffic elimination, microarchitecture, out-of-order execution, memory latency, register renaming, vector architecture, precise interrupts
2	Keith I. Farkas, Norman P. Jouppi, Paul Chow	Register File Design Considerations in Dynamically Scheduled Processors.	HPCA	1996	DBLP DOI BibTeX RDF	dynamic scheduling, register files, register renaming
2	M. Anton Ertl, Andreas Krall	Removing Anti Dependences by Repairing.	CC	1996	DBLP DOI BibTeX RDF	anti dependence, instruction-level parallelism, speculative execution, repairing, register renaming
2	Eric Sprangle, Yale N. Patt	Facilitating superscalar processing via a combined static/dynamic register renaming scheme.	MICRO	1994	DBLP DOI BibTeX RDF	superscalar processors, out-of-order execution, register renaming, predicated execution
1	Elham Safi, Andreas Moshovos, Andreas G. Veneris	Two-Stage, Pipelined Register Renaming.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Fakhar Anjam, Stephan Wong, Faisal Nadeem	A multiported register file with register renaming for configurable softcore VLIW processors.	FPT	2010	DBLP DOI BibTeX RDF
1	Jungwook Kim, Seong Tae Jhang, Chu Shik Jhon	Dynamic register-renaming scheme for reducing power-density and temperature.	SAC	2010	DBLP DOI BibTeX RDF	embedded operating systems for mobile computing, power-density minimization, renaming scheme, register file, thermal management
1	Kaveh Aasaraai, Andreas Moshovos	Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming.	FPL	2009	DBLP DOI BibTeX RDF
1	Hui Zeng, Kanad Ghose, Dmitry Ponomarev	Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures.	ICPP	2009	DBLP DOI BibTeX RDF
1	Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay	Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor.	ISCA	2009	DBLP DOI BibTeX RDF	checkpoint-based architecture, hardware speculation, sst, chip multiprocessor, cmp, instruction-level parallelism, processor architecture, memory-level parallelism
1	Hui Zeng, Matt T. Yourst, Kanad Ghose	An energy-efficient checkpointing mechanism for out of order commit processor.	ISLPED	2009	DBLP DOI BibTeX RDF	checkpoint, microprocessor
1	Suriya Subramanian, Kathryn S. McKinley	HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Maziar Goudarzi, Tohru Ishihara	Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asymmetric sram, leakage, instruction cache, register renaming
1	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
1	Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero	Microarchitectural Support for Speculative Register Renaming.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Wann-Yun Shieh, Chang-Yi Lee	Power-aware Register Renaming for Multi-banked Register Files.	ESA	2007	DBLP BibTeX RDF
1	Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni	On the latency, energy and area of checkpointed, superscalar register alias tables.	ISLPED	2007	DBLP DOI BibTeX RDF	latency, checkpointing, energy, register renaming
1	Shuai Wang, Hongyan Yang, Jie S. Hu, Sotirios G. Ziavras	Asymmetrically Banked Value-Aware Register Files.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Xuehai Qian, He Huang, Hao Zhang, Guoping Long, Junchao Zhang, Dongrui Fan	Design and Implementation of Floating Point Stack on General RISC Architecture.	PDP	2007	DBLP DOI BibTeX RDF
1	Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero	Speculative early register release.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	physical register release, optimization, register file, register renaming
1	Mehrdad Reshadi, Bita Gorjiara, Nikil D. Dutt	Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Rama Sangireddy	Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Wide-issue processors, integer pipeline, rename logic complexity, front-end power consumption
1	Taqi N. Buti, Robert G. McDonald, Zakaria Khwaja, Asit Ambekar, Hung Q. Le, William E. Burky, Bert Williams	Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors.	IBM Journal of Research and Development	2005	DBLP BibTeX RDF
1	Hua Yang, Gang Cui, Xiao-Zong Yang	2L-MuRR: A Compact Register Renaming Scheme for SMT Processors.	ISPA	2005	DBLP DOI BibTeX RDF
1	Weiwu Hu, Fuxin Zhang, Zusong Li	Microarchitecture of the Godson-2 Processor.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming
1	Hua Yang, Gang Cui, Xiaozong Yang	Eliminating Inter-Thread Interference in Register File for SMT Processors.	PDCAT	2005	DBLP DOI BibTeX RDF
1	Emil Talpes, Diana Marculescu	Execution cache-based microarchitecture for power-efficient superscalar processors.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Roope Kaivola	Formal Verification of Pentium® 4 Components with Symbolic Simulation and Inductive Invariants.	CAV	2005	DBLP DOI BibTeX RDF
1	Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao	Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops.	CGO	2004	DBLP DOI BibTeX RDF
1	Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin	Scheduling Reusable Instructions for Power Reduction.	DATE	2004	DBLP DOI BibTeX RDF
1	Vinod Viswanath	Multi-log Processor - Towards Scalable Event-Driven Multiprocessors.	DSD	2004	DBLP DOI BibTeX RDF
1	Jamison D. Collins, Dean M. Tullsen	Clustered Multithreaded Architectures - Pursuing both IPC and Cycle Time.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Liem Tran, Nicholas Nelson, Fung Ngai, Steve Dropsho, Michael C. Huang	Dynamically reducing pressure on the physical register file through simple register sharing.	ISPASS	2004	DBLP DOI BibTeX RDF
1	Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose	Complexity-Effective Reorder Buffer Designs for Superscalar Processors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
1	Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero	Late Allocation and Early Release of Physical Registers.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
1	Zhenyu Liu, Jiayue Qi	A Novel Rename Register Architecture and Performance Analysis.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
1	Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood, Brad Calder	Reducing code size with echo instructions.	CASES	2003	DBLP DOI BibTeX RDF	code size optimization, echo instructions, compression
1	Gang-Ryung Uh	Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer.	SCOPES	2003	DBLP DOI BibTeX RDF
1	Vlad Petric, Anne Bracy, Amir Roth	Three extensions to register integration.	MICRO	2002	DBLP DOI BibTeX RDF
1	André Seznec, Eric Toullec, Olivier Rochecouste	Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors.	MICRO	2002	DBLP DOI BibTeX RDF
1	Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero	Hardware Schemes for Early Register Release. (PDF / PS)	ICPP	2002	DBLP DOI BibTeX RDF
1	Lori Carter, Weihaw Chuang, Brad Calder	An EPIC Processor with Pending Functional Units.	ISHPC	2002	DBLP BibTeX RDF
1	David May, Henk L. Muller, Nigel P. Smart	Random Register Renaming to Foil DPA.	CHES	2001	DBLP DOI BibTeX RDF
1	Alessandro De Gloria, Mauro Olivieri	An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Perry H. Wang, Hong Wang 0003, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen	Register Renaming and Scheduling for Dynamic Execution of Predicated Code.	HPCA	2001	DBLP DOI BibTeX RDF
1	M. Watheq El-Kharashi, Fayez El Guibaly, Kin F. Li	Adapting Tomasulo's algorithm for bytecode folding based Java processors.	SIGARCH Computer Architecture News	2001	DBLP DOI BibTeX RDF	instruction shelving, java bytecode folding, java stack folding, reservation stations, stack processors, tomasulo's algorithm, java, Java, java virtual machine, dynamic scheduling, java processors, register renaming
1	Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori	A high-speed dynamic instruction scheduling scheme for superscalar processors.	MICRO	2001	DBLP DOI BibTeX RDF
1	Tony Werner, Venkatesh Akella	An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals	Dynamic Register Renaming Through Virtual-Physical Registers.	J. Instruction-Level Parallelism	2000	DBLP BibTeX RDF
1	Daniel Tate, Gordon Steven, Fleur L. Steven	Static Scheduling for Out-of-order Instruction Issue Processors.	ACAC	2000	DBLP DOI BibTeX RDF
1	Bruce R. Childers, Jack W. Davidson	Architectural Considerations for Application-Specific Counterflow Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Application-specific integrated processors, counterflow pipelines, architectural synthesis
1	David W. Lloyd, Jim D. Garside, D. A. Gilbert	Memory Faults in Asynchronous Microprocessors.	ASYNC	1999	DBLP DOI BibTeX RDF
1	C. John Glossner, Stamatis Vassiliadis	Delft-Java Dynamic Translation.	EUROMICRO	1999	DBLP DOI BibTeX RDF
1	Madhavi Gopal Valluri, R. Govindarajan	Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Out-of-order Issue Processors, Instruction-Level Parallelism, Register Allocation, Instruction Scheduling, Integrated Methods
1	A. Pita, Nadeem Malik	Sectored renaming for superscalar microprocessors.	IPCCC	1999	DBLP DOI BibTeX RDF
1	Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, Dean M. Tullsen	Software-Directed Register Deallocation for Simultaneous Multithreaded Processors.	IEEE Trans. Parallel Distrib. Syst.	1999	DBLP DOI BibTeX RDF	architecture, register file, simultaneous multithreading, Multithreaded architecture
1	Ramaswamy Govindarajan, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors.	LCPC	1999	DBLP DOI BibTeX RDF
1	Artur Klauser, Abhijit Paithankar, Dirk Grunwald	Selective Eager Execution on the PolyPath Architecture.	ISCA	1998	DBLP DOI BibTeX RDF
1	John Matthews, Byron Cook, John Launchbury	Microprocessor Specification in Hawk. (PDF / PS)	ICCL	1998	DBLP DOI BibTeX RDF	Microprocessor Verification, Domain-Specific Language, Functional Language, Hardware Verification
1	Sylvain Lelait, Guang R. Gao, Christine Eisenbeis	A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops.	CC	1998	DBLP DOI BibTeX RDF
1	Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao	A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors.	IEEE PACT	1997	DBLP DOI BibTeX RDF	Scheduling, register renaming, out-of-order issue, Register Pressure
1	Subbarao Palacharla, Norman P. Jouppi, James E. Smith	Complexity-Effective Superscalar Processors.	ISCA	1997	DBLP DOI BibTeX RDF
1	Sriram Vajapeyam, Tulika Mitra	Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences.	ISCA	1997	DBLP DOI BibTeX RDF
1	Mayan Moudgill, Keshav Pingali, Stamatis Vassiliadis	Register renaming and dynamic speculation: an alternative approach.	MICRO	1993	DBLP DOI BibTeX RDF