Search results for "repeater insertion"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Ja Chun Ku, Yehea I. Ismail	Thermal-aware methodology for repeater insertion in low-power VLSI circuits.	ISLPED	2007	DBLP DOI BibTeX RDF	low-power design, repeater insertion, temperature-aware design
3	Salim Chowdhury, John Lillis	Repeater insertion for concurrent setup and hold time violations with power-delay trade-off.	ISPD	2007	DBLP DOI BibTeX RDF	early-mode timing, hold violation, late-mode timing, setup violation, timing optimization, repeater insertion
3	Yuantao Peng, Xun Liu	Low-power repeater insertion with both delay and slew rate constraints.	DAC	2006	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion, slew rate
3	Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors	Accounting for the skin effect during repeater insertion.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	buffer design, optimization, delay, power, repeater insertion, skin effect
3	Yuantao Peng, Xun Liu	A sensitivity analysis of low-power repeater insertion.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, sensitivity, repeater insertion
3	Yuantao Peng, Xun Liu	Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method.	DAC	2005	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion
3	Yuantao Peng, Xun Liu	Power macromodeling of global interconnects considering practical repeater insertion.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, interconnect, macromodeling, repeater insertion
3	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou	Practical repeater insertion for low power: what repeater library do we need?	DAC	2004	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion
3	Dinesh Pamunuwa, Hannu Tenhunen	On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	Cross-talk, Delay minimisation, Static timing, Repeater insertion, Deep sub-micron
2	Renatas Jakushokas, Eby G. Friedman	Simultaneous shield and repeater insertion.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	delay, interconnects, noise, power, area
2	Ashutosh Chakraborty, David Z. Pan	On stress aware active area sizing, gate sizing, and repeater insertion.	ISPD	2009	DBLP DOI BibTeX RDF	performance, buffer, sizing, stress, repeater
2	Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli	Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits.	NanoNet	2009	DBLP DOI BibTeX RDF	timing optimization, on-chip interconnect, repeater insertion, 3-D ICs
2	Charbel J. Akl, Magdy A. Bayoumi	Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Nikolai Ryzhenko, Oleg Venger	A practical repeater insertion flow.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	physical design, buffer insertion, fanout optimization, topology generation
2	DiaaEldin Khalil, Yehea I. Ismail	A global interconnect link design for many-core microprocessors.	IFMT	2008	DBLP DOI BibTeX RDF	interconnect, link, bus, repeater insertion
2	Ja Chun Ku, Yehea I. Ismail	Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Hanif Fatemi, Behnam Amelifard, Massoud Pedram	Power optimal MTCMOS repeater insertion for global buses.	ISLPED	2007	DBLP DOI BibTeX RDF	MTCMOS circuits, low-power design, buffer insertion
2	Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Hendrik F. Hamann, Alan J. Weger, Pradip Bose	Thermal-aware task scheduling at the system software level.	ISLPED	2007	DBLP DOI BibTeX RDF	low-power design, repeater insertion, temperature-aware design
2	Yuantao Peng, Xun Liu	An Efficient Low-Power Repeater-Insertion Scheme.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou	Practical repeater insertion for low power: what repeater library do we need?	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai	Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion.	ICICIC	2006	DBLP DOI BibTeX RDF
2	Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo	A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Vinita V. Deodhar, Jeffrey A. Davis	Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
2	Yuantao Peng, Xun Liu	RITC: Repeater Insertion with Timing Target Compensation.	ISVLSI	2005	DBLP DOI BibTeX RDF
2	Yu Ching Chang, King Ho Tam, Lei He	Power-optimal repeater insertion considering Vdd and Vth as design freedoms.	ISLPED	2005	DBLP DOI BibTeX RDF	low power, buffer insertion
2	Srinivasa R. Sridhara, Naresh R. Shanbhag	A low-power bus design using joint repeater insertion and coding.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power, coding, crosstalk, repeaters
2	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou	RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power.	DATE	2005	DBLP DOI BibTeX RDF
2	Prashant Saxena, Bill Halpin	Modeling repeaters explicitly within analytical placement.	DAC	2004	DBLP DOI BibTeX RDF	interconnect, placement, scaling, buffering, repeater insertion, force-directed placement, analytical placement
2	Srividya Srinivasaraghavan, Wayne Burleson	Interconnect Effort - A Unification of Repeater Insertion and Logical Effort.	ISVLSI	2003	DBLP DOI BibTeX RDF
2	Vinita V. Deodhar, Jeffrey A. Davis	Voltage scaling and repeater insertion for high-throughput low-power interconnects.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu	Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
2	Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao	Flip-Flop and Repeater Insertion for Early Interconnect Planning.	DATE	2002	DBLP DOI BibTeX RDF
2	Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie	Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion.	ISQED	2001	DBLP DOI BibTeX RDF
2	Dinesh Pamunuwa, Hannu Tenhunen	Repeater Insertion To Minimise Delay In Coupled Interconnects.	VLSI Design	2001	DBLP DOI BibTeX RDF
2	Yehea I. Ismail, Eby G. Friedman	Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
2	Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl	Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion.	ISLPED	2000	DBLP DOI BibTeX RDF
2	John Lillis, Chung-Kuan Cheng	Timing optimization for multisource nets: characterization andoptimal repeater insertion.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
2	Noel Menezes, Chung-Ping Chen	Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.	VLSI Design	1999	DBLP DOI BibTeX RDF
2	Yehea I. Ismail, Eby G. Friedman	Repeater insertion in RLC lines for minimum propagation delay.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Repeater insertion in tree structured inductive interconnect.	ICCAD	1999	DBLP BibTeX RDF
2	P. Ghosh, R. Mangaser, C. Mark, K. Rose	Interconnect-Dominated VLSI Design.	ARVLSI	1999	DBLP DOI BibTeX RDF	Microprocessor Performance Estimation, Interconnects, Floorplanning, VLSI Design, Repeater Insertion
2	John Lillis, Chung-Kuan Cheng	Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion.	DAC	1997	DBLP DOI BibTeX RDF
1	Shaloo Rakheja, Azad Naeemi	Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits.	ISQED	2012	DBLP DOI BibTeX RDF
1	Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria	Repeater insertion in power-managed VLSI systems.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Renatas Jakushokas, Eby G. Friedman	Resource Based Optimization for Simultaneous Shield and Repeater Insertion.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Renatas Jakushokas, Eby G. Friedman	Minimizing Noise Via Shield and Repeater Insertion.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen	Fast buffering for optimizing worst slack and resource consumption in repeater trees.	ISPD	2009	DBLP DOI BibTeX RDF	interconnect buffering, repeater tree, physical design, repeater insertion, timing closure
1	Falah R. Awwad, Mohamed Nekili, Venkatanarayana Ramachandran, Mohamad Sawan	On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Vinita V. Deodhar, Jeffrey A. Davis	Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Timing optimization in logic with interconnect.	SLIP	2008	DBLP DOI BibTeX RDF	interconnect, logic circuits, timing optimization, repeaters, logical effort
1	Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng	On-chip high performance signaling using passive compensation.	ICCD	2008	DBLP DOI BibTeX RDF
1	Himanshu Kaul, Jae-sun Seo, Mark Anders, Dennis Sylvester, Ram Krishnamurthy	A robust alternate repeater technique for high performance busses in the multi-core era.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Qingli Zhang, Jinxiang Wang, Yizheng Ye	Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Rajeevan Chandel, Sankar Sarkar, Rajendra Prasad Agarwal	An analysis of interconnect delay minimization by low-voltage repeater insertion.	Microelectronics Journal	2007	DBLP DOI BibTeX RDF
1	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou	RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power	CoRR	2007	DBLP BibTeX RDF
1	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	bit transitions, bus-encoding scheme, high impedance state, simultaneous switching noise (SSN), spatial and temporal redundancy, low power, delay, encoder, decoder, crosstalk noise, inductive coupling
1	Jonathan Rosenfeld, Eby G. Friedman	Quasi-Resonant Interconnects: A Low Power Design Methodology.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Charbel J. Akl, Magdy A. Bayoumi	Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion.	ISQED	2007	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Sherief Reda, Puneet Sharma	On-Line Adjustable Buffering for Runtime Power Reduction.	ISQED	2007	DBLP DOI BibTeX RDF
1	Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas	Glitch Control with Dynamic Receiver Threshold Adjustment.	ISQED	2007	DBLP DOI BibTeX RDF
1	Ja Chun Ku, Yehea I. Ismail	On the Scaling of Temperature-Dependent Effects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Atul Maheshwari, Wayne Burleson	Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Liang Zhang, J. M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon	Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao	Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Qingli Zhang, Jinxiang Wang, Yizheng Ye	An energy-efficient temporal encoding circuit technique for on-chip high performance buses.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	on-chip buses, energy-efficient, encoding, repeaters
1	W. T. Cheung, N. Wong	Power optimization in a repeater-inserted interconnect via geometric programming.	ISLPED	2006	DBLP DOI BibTeX RDF	optimization, interconnect, power, repeater, geometric programming
1	Prashant Saxena	On controlling perturbation due to repeaters during quadratic placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann	Memory performance prediction for high-performance microprocessors at deep submicrometer technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Guoqing Chen, Eby G. Friedman	Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny	Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Vineet Wason, Kaustav Banerjee	A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	buffer-interconnect system, statistical delay and power models, sensitivity analysis, parameter variations, statistical optimization
1	Radu M. Secareanu, S. K. Banerjee, Olin L. Hartin, Francisco V. Fernández, Eby G. Friedman	Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Liang Zhang, John Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon	Driver pre-emphasis techniques for on-chip global buses.	ISLPED	2005	DBLP DOI BibTeX RDF	current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus
1	Krishnan Sundaresan, Nihar R. Mahapatra	Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses.	HPCA	2005	DBLP DOI BibTeX RDF
1	Guoqing Chen, Eby G. Friedman	Low power repeaters driving RLC interconnects with delay and bandwidth constraints.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias	A distributed FIFO scheme for on chip communication.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng	Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.	ISQED	2005	DBLP DOI BibTeX RDF
1	Jinwook Jang, Sheng Xu, Wayne Burleson	Jitter in Deep Sub-Micron Interconnect.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Vinita V. Deodhar, Jeffrey A. Davis	Optimization of throughput performance for low-power VLSI interconnects.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for system-on-chip networks: a unified framework.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Nisar Ahmed, Mohammad H. Tehranipour, Dian Zhou, Mehrdad Nourani	Frequency driven repeater insertion for deep submicron.	ISCAS	2004	DBLP BibTeX RDF
1	V. Seth, Min Zhao, Jiang Hu	Exploiting level sensitive latches in wire pipelining.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Atul Maheshwari, Wayne P. Burleson	Differential current-sensing for on-chip interconnects.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	André K. Nieuwland, Atul Katoch, Maurice Meijer	Reducing Cross-Talk Induced Power Consumption and Delay.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Pasquale Cocchini	A methodology for optimal repeater insertion in pipelined interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten	Simultaneous Analytic Area and Power Optimization for Repeater Insertion.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Magdy A. El-Moursy, Eby G. Friedman	Optimum wire sizing of RLC interconnect with repeaters.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect
1	Atul Maheshwari, Wayne Burleson	Repeater and current-sensing hybrid circuits for on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	interconnect circuits, delay, power, area
1	Weiping Liao, Lei He	Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Ruibing Lu, Cheng-Kok Koh	Interconnect Planning with Local Area Constrained Retiming.	DATE	2003	DBLP DOI BibTeX RDF
1	Nataraj Akkiraju, Mosur Mohan	Spec Based Flip-Flop And Buffer Insertion.	ICCD	2003	DBLP DOI BibTeX RDF
1	Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham	Buffer insertion with adaptive blockage avoidance.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas	A Dynamically Tunable Memory Hierarchy.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures
1	Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III	Current-mode signaling in deep submicrometer global interconnects.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Hannu Tenhunen, Dinesh Pamunuwa	On dynamic delay and repeater insertion.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Pasquale Cocchini	Concurrent flip-flop and repeater insertion for high performance integrated circuits.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Harshit K. Shah, Pun Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis	Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl	A physical model for the transient response of capacitively loaded distributed rlc interconnects.	DAC	2002	DBLP DOI BibTeX RDF	distributed rlc lines, overshoot, interconnects, crosstalk, time delay, repeaters, transient response
1	Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen	Optimising bandwidth over deep sub-micron interconnect.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Gregorio Cappuccino, Giuseppe Cocorullo	Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.	PATMOS	2002	DBLP DOI BibTeX RDF