Search results for "resource binding"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Enric Musoll, Jordi Cortadella	Scheduling and resource binding for low power.	ISSS	1995	DBLP DOI BibTeX RDF	data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding
3	Jason Cong, Yiping Fan, Junjuan Xu	Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	distributed register file, Behavioral synthesis, resource binding
3	Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu	Optimality study of resource binding with multi-Vdds.	DAC	2006	DBLP DOI BibTeX RDF	low power design, behavioral synthesis, resource binding
3	Jason Cong, Yiping Fan, Wei Jiang	Platform-based resource binding using a distributed register-file microarchitecture.	ICCAD	2006	DBLP DOI BibTeX RDF	distributed register file, behavior synthesis, resource binding
2	Yibo Chen, Jin Ouyang, Yuan Xie	ILP-based scheme for timing variation-aware scheduling and resource binding.	SoCC	2008	DBLP DOI BibTeX RDF
2	Azadeh Davoodi, Ankur Srivastava	Power-driven simultaneous resource binding and floorplanning: a probabilistic approach.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Azadeh Davoodi, Ankur Srivastava	Simultaneous floorplanning and resource binding: a probabilistic approach.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Eren Kursun, Ankur Srivastava, Seda Ogrenci Memik, Majid Sarrafzadeh	Early evaluation techniques for low power binding.	ISLPED	2002	DBLP DOI BibTeX RDF	metric evaluation, scheduling, low power design, resource binding
2	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	Multiple-Wordlength Resource Binding.	FPL	2000	DBLP DOI BibTeX RDF
2	Honda Shing, Lionel M. Ni	Resource binding - a universal approach to parallel programming.	SC	1990	DBLP BibTeX RDF
1	Keisuke Inoue, Mineo Kaneko	Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Kartikey Mittal, Arpit Joshi, Madhu Mutyam	Timing variation-aware scheduling and resource binding in high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Jongyoon Jung, Taewhan Kim	Scheduling and Resource Binding Algorithm Considering Timing Variation.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Akinori Saito, Takumi Kusanagi, Koichiro Ochimizu	A Simultaneous Project Scheduling and Resource Binding Method Based on the Load-Capacity Model.	APSEC	2011	DBLP DOI BibTeX RDF
1	Mineo Kaneko, Keisuke Inoue	Ordered coloring-based resource binding for datapaths with improved skew-adjustability.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Vincenzo Ciancia, Alexander Kurz, Ugo Montanari	Families of Symmetries as Efficient Models of Resource Binding.	Electr. Notes Theor. Comput. Sci.	2010	DBLP DOI BibTeX RDF
1	Yibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach	Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Zigang Xiao, Evangeline F. Y. Young	Droplet-routing-aware module placement for cross-referencing biochips.	ISPD	2010	DBLP DOI BibTeX RDF	cross-referencing, dmfb, synthesis, placement, microfluidics, biochip
1	Deming Chen, Scott Cromar	An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Shahin Golshan, Eli Bozorgzadeh	SEU-aware resource binding for modular redundancy based designs on FPGAs.	DATE	2009	DBLP BibTeX RDF
1	Shih-Hsu Huang, Chun-Hua Cheng	Timing driven power gating in high-level synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Junbo Yu, Qiang Zhou, Jinian Bian	Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Elena Maftei, Paul Pop, Jan Madsen	Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips.	CASES	2009	DBLP DOI BibTeX RDF	reconfigurability, microfluidics, biochips
1	Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki	SAT-based resource binding for reducing critical path delays.	FPL	2008	DBLP DOI BibTeX RDF
1	Jason Cong, Wei Jiang	Pattern-based behavior synthesis for FPGA resource reduction.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, pattern, behavior synthesis
1	Jason Cong, Junjuan Xu	Simultaneous FU and Register Binding Based on Network Flow Method.	DATE	2008	DBLP DOI BibTeX RDF
1	Jason Cong	A new generation of C-base synthesis tool and domain-specific computing.	SoCC	2008	DBLP DOI BibTeX RDF
1	Vyas Krishnan, Srinivas Katkoori	Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi	Low test application time resource binding for behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	CDFG, high-level synthesis, Testability, test synthesis
1	Jongyoon Jung, Taewhan Kim	Timing variation-aware high-level synthesis.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim	Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture.	DAC	2007	DBLP DOI BibTeX RDF
1	Vyas Krishnan, Srinivas Katkoori	A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
1	Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou	Unified Incremental Physical-Level and High-Level Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Min Ni, Seda Ogrenci Memik	Thermal-induced leakage power optimization by redundant resource allocation.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Mineo Kaneko	Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Fred Ma, John P. Knight, Calvin Plett	Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithms.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou	Incremental exploration of the combined physical and behavioral design space.	DAC	2005	DBLP DOI BibTeX RDF	high-level synthesis, floorplan, incremental
1	Fei Su, Krishnendu Chakrabarty	Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips.	DAC	2005	DBLP DOI BibTeX RDF	synthesis, placement, defect tolerance, microfluidics, biochip
1	Koji Ohashi, Mineo Kaneko	Statistical Analysis Driven Synthesis of Asynchronous Systems.	ICCD	2005	DBLP DOI BibTeX RDF
1	Xiaoning Wang, Lijuan Xiao, Wei Li 0008, Zhiwei Xu	Abacus: A Service-Oriented Programming Language for Grid Applications.	IEEE SCC	2005	DBLP DOI BibTeX RDF
1	Koji Ohashi, Mineo Kaneko	Statistical schedule length analysis in asynchronous datapath synthesis.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh	On effective slack management in postscheduling phase.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Partha Biswas, Nikil D. Dutt	Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction
1	Guowen Wu, Liang Zhang, Yin Kang, Jun Yin, Xiangdong Zhou, Peiyi Zhang, Lin Zhao	A Metasearch Engine with Automatic Resource Binding Ability.	ICADL	2004	DBLP DOI BibTeX RDF
1	Fred Ma, John P. Knight, Calvin Plett	Physical Resource Binding for a Coarse Grain Reconfigurable Array.	ERSA	2004	DBLP BibTeX RDF
1	Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava	High level techniques for power-grid noise immunity.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	high-level noise-immune optimization
1	David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee	Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
1	Chang Huang, Zhaohui Wu, Guozhou Zheng	A Negotiation Protocol for Database Resource Binding.	ISPDC	2003	DBLP DOI BibTeX RDF
1	Nattawut Thepayasuwan, Hua Tang, Alex Doboli	An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Paolo Bellavista, Antonio Corradi, Rebecca Montanari, Cesare Stefanelli	Policy-Driven Binding to Information Resources in Mobility-Enabled Scenarios.	Mobile Data Management	2003	DBLP DOI BibTeX RDF
1	Per Bjuréus, Mikael Millberg, Axel Jantsch	FPGA resource and timing estimation from Matlab execution traces.	CODES	2002	DBLP DOI BibTeX RDF	FPGA, estimation, Matlab, MATLAB, design exploration
1	Mehrdad Nourani, Christos A. Papachristou	False path exclusion in delay analysis of RTL structures.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu	Efficient design exploration based on module utility selection.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Flavius Gruian, Krzysztof Kuchcinski	Operation Binding and Scheduling for Low Power Using Constraint Logic Programming.	EUROMICRO	1998	DBLP DOI BibTeX RDF
1	Birger Landwehr, Peter Marwedel, Rainer Dömer	OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming.	EURO-DAC	1994	DBLP DOI BibTeX RDF