Search results for "retiming"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek	Post-placement C-slow retiming for the xilinx virtex FPGA.	FPGA	2003	DBLP DOI BibTeX RDF	C-slow retiming, FPGA CAD, FPGA optimization, retiming
4	Hans-Georg Martin	Retiming for Circuits with Enable Registers.	EUROMICRO	1996	DBLP DOI BibTeX RDF	enable registers, circuit retiming, combinational paths, D-Flipflops, retiming algorithm, sequential elements, high level synthesis, high level synthesis, digital circuits
3	Smita Krishnaswamy, Igor L. Markov, John P. Hayes	Improving testability and soft-error resilience through retiming.	DAC	2009	DBLP DOI BibTeX RDF	testability, soft errors, retiming
3	Hai Zhou	A new efficient retiming algorithm derived by formal manipulation.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Clockperiod minimization, algorithm derivation, retiming
3	Yu Hu, Yan Lin, Lei He, Tim Tuan	Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, Low power, retiming
3	In-Ho Moon	Compositional verification of retiming and sequential optimizations.	DAC	2008	DBLP DOI BibTeX RDF	conditional equivalence, retime offset, sequential equivalence, retiming, compositional verification
3	Jia Wang, Hai Zhou	An efficient incremental algorithm for min-area retiming.	DAC	2008	DBLP DOI BibTeX RDF	retiming
3	Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton	Fast Minimum-Register Retiming via Binary Maximum-Flow.	FMCAD	2007	DBLP DOI BibTeX RDF	Sequential Verification, Retiming, Maximum Flow, State Minimization
3	Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee	Retiming for Synchronous Data Flow Graphs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	cycle length, synchronous data flow graphs, retiming
3	Mongkol Ekpanyapong, Sung Kyu Lim	Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization.	ISPD	2006	DBLP DOI BibTeX RDF	supply and threshold voltage scaling, low power design, retiming
3	Yu Hu, Yan Lin, Lei He, Tim Tuan	Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.	DAC	2006	DBLP DOI BibTeX RDF	FPGA, low power, retiming
3	Chuan Lin, Hai Zhou	An efficient retiming algorithm under setup and hold constraints.	DAC	2006	DBLP DOI BibTeX RDF	retiming
3	Timothy W. O'Neil, Edwin Hsing-Mean Sha	Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	scheduling, graph transformation, retiming, unfolding, data-flow graphs, timing optimization
3	Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown	Incremental retiming for FPGA physical synthesis.	DAC	2005	DBLP DOI BibTeX RDF	FPGA, retiming, physical synthesis
3	Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha	Iterational retiming: maximize iteration-level parallelism for nested loops.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	optimization, partition, retiming, nested loops
3	Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi	A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	Minimum area retiming, application of mincost network flow, longpath circuit constraints, minimum delay padding, shortpath circuit constraints
3	Noureddine Chabini, Wayne Wolf	An approach for integrating basic retiming and software pipelining.	EMSOFT	2004	DBLP DOI BibTeX RDF	embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size
3	Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge	Reducing pipeline energy demands with local DVS and dynamic retiming.	ISLPED	2004	DBLP DOI BibTeX RDF	dynamic retiming with global DVS, local DVS, razor
3	Jia Wang, Hai Zhou	Minimal period retiming under process variations.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	process variations, retiming, statistical timing analysis
3	Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria	Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	supply voltage scaling, performance, power consumption, CMOS, retiming, digital design
3	Jason Cong, Xin Yuan	Multilevel global placement with retiming.	DAC	2003	DBLP DOI BibTeX RDF	physical hierarchy, placement, retiming, deep sub-micron
3	Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz	Accelerating Retiming Under the Coupled-Edge Timing Model.	ISVLSI	2002	DBLP DOI BibTeX RDF	retiming, timing optimization
3	Yu-Lung Hsu, Sying-Jyan Wang	Retiming-based logic synthesis for low-power.	ISLPED	2002	DBLP DOI BibTeX RDF	switching actvity, low-power, logic design, retiming
3	Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer	Minimum-power retiming for dual-supply CMOS circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	dual-supply, retiming theory, low-power, synthesis, low-power design
3	Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski	Retiming-based factorization for sequential logic optimization.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	finite stat machines, retiming, sequential synthesis
3	Zulan Huang, Yizheng Ye, Zhigang Mao	A New Algorithm for Retiming-Based Partial Scan.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	retiming, Partial scan, minimum feedback vertex set
3	Pierre-Yves Calland, Alain Darte, Yves Robert	Circuit Retiming Applied to Decomposed Software Pipelining.	IEEE Trans. Parallel Distrib. Syst.	1998	DBLP DOI BibTeX RDF	circuit retiming, Software pipelining, list scheduling, modulo scheduling, cyclic scheduling
3	Otmane Aït Mohamed, Eduard Cerny, Xiaoyu Song	MDG-based Verification by Retiming and Combinational Transformations.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Circuit Transformations, Non-termination, Formal Verification, Retiming, Multiway Decision Graphs
3	Naresh Maheshwari, Sachin S. Sapatnekar	Efficient Minarea Retiming of Large Level-Clocked Circuits.	DATE	1998	DBLP DOI BibTeX RDF	Level-clocked, Optimization, Synthesis, Retiming, Area
3	Liang-Fang Chao, Edwin Hsing-Mean Sha	Scheduling Data-Flow Graphs via Retiming and Unfolding.	IEEE Trans. Parallel Distrib. Syst.	1997	DBLP DOI BibTeX RDF	scheduling, parallel processing, retiming, unfolding, Data-flow graphs, loop parallelization
3	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Synthesis of Sequential Circuits by Redundancy Removal and Retiming.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	synthesis of sequential circuits, sequentially redundant fault, retiming, redundant fault, redundancy removal
3	Naresh Maheshwari, Sachin S. Sapatnekar	Minimum area retiming with equivalent initial states.	ICCAD	1997	DBLP DOI BibTeX RDF	VLSI, Sequential Circuits, Retiming, Design Automation, Timing Optimization, Area Optimization
3	Nelson L. Passos, Edwin Hsing-Mean Sha	Achieving Full Parallelism Using Multidimensional Retiming.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	multidimensional data-flow graphs, instruction level parallelism, VLIW, Retiming, loop transformation, superscalar, nested loops
3	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
3	Debesh Kumar Das, Bhargab B. Bhattacharya	Does retiming affect redundancy in sequential circuits?	VLSI Design	1996	DBLP DOI BibTeX RDF	combinational redundancy, sequential redundancy, fault diagnosis, logic testing, timing, redundancy, test generation, design for testability, sequential circuits, sequential circuit, fault, retiming, logic optimization, operation speed
3	Vigyan Singhal, Sharad Malik, Robert K. Brayton	The case for retiming with explicit reset circuitry.	ICCAD	1996	DBLP DOI BibTeX RDF	reset state, synchronous reset, asynchronous reset, Retiming, initial state
3	Naresh Maheshwari, Sachin S. Sapatnekar	A Practical Algorithm for Retiming Level-Clocked Circuits. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	level-clocked, retiming, clock skew, timing optimization
3	Kumar N. Lalgudi, Marios C. Papaefthymiou	Efficient retiming under a general delay model.	ARVLSI	1995	DBLP DOI BibTeX RDF	retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays
3	Larry R. Dennison, William J. Dally, Thucydides Xanthopoulos	Low-latency plesiochronous data retiming.	ARVLSI	1995	DBLP DOI BibTeX RDF	telecommunication signalling, data retiming, plesiochronous data, support circuitry, undirectional signalling, timing, latency, communication networks, routers, telecommunication network routing, repeaters, repeaters, bridges, hubs
3	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, transformation, timing, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
3	Samir Lejmi, Bozena Kaminska, Bechir Ayari	Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudo-exhaustive testing
3	Sven Simon, Ralf Bucher, Josef A. Nossek	Retiming of synchronous circuits with variable topology.	VLSI Design	1995	DBLP DOI BibTeX RDF	variable topology, combinational elements selection, circuit graph, optimization, graph theory, linear programming, delays, timing, interconnections, logic design, network topology, logic CAD, retiming, circuit CAD, circuit optimisation, synchronous circuits
3	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
2	Hai Zhou	Retiming and resynthesis with sweep are complete for sequential transformation.	FMCAD	2009	DBLP DOI BibTeX RDF
2	Dmitry Bufistov, Jordi Cortadella, Marc Galceran Oms, Jorge Júlvez, Michael Kishinevsky	Retiming and recycling for elastic systems with early evaluation.	DAC	2009	DBLP DOI BibTeX RDF	early evaluation, elastic systems, optimization
2	Jia Wang, Hai Zhou	Risk aversion min-period retiming under process variations.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee	Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Duo Liu, Zili Shao, Meng Wang, Minyi Guo, Jingling Xue	Optimal loop parallelization for maximizing iteration-level parallelism.	CASES	2009	DBLP DOI BibTeX RDF	iteration-level parallelism, retiming, loop transformation, loop parallelization, data dependence graph
2	Hui Liu, Zili Shao, Meng Wang, Junzhao Du, Chun Jason Xue, Zhiping Jia	Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Periodic dependent tasks, Scheduling, Multimedia, Real-time, Dynamic voltage scaling (DVS), Multi-core, Software pipelining, Retiming
2	Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton	Scalable min-register retiming under timing and initializability constraints.	DAC	2008	DBLP DOI BibTeX RDF	min-area, retiming, initial state, sequential optimization
2	Kenneth Eguro, Scott Hauck	Simultaneous Retiming and Placement for Pipelined Netlists.	FCCM	2008	DBLP DOI BibTeX RDF
2	Lei Wang 0011, Zhiying Wang, Kui Dai	Performance Bound Analysis and Retiming of Timed Circuits.	ICYCS	2008	DBLP DOI BibTeX RDF
2	Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu	Wire Retiming Problem With Net Topology Optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Cristian Soviani, Olivier Tardieu, Stephen A. Edwards	Optimizing Sequential Cycles Through Shannon Decomposition and Retiming.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Mongkol Ekpanyapong, Xin Zhao, Sung Kyu Lim	An Efficient Computation of Statistically Critical Sequential Paths Under Retiming.	ASP-DAC	2007	DBLP DOI BibTeX RDF
2	Khurram Waheed, Robert B. Staszewski, John L. Wallberg	Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Jie-Hong Roland Jiang, Wei-Lun Hung	Inductive equivalence checking under retiming and resynthesis.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Ming Su, Lili Zhou, C.-J. Richard Shi	Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.	ICCD	2007	DBLP DOI BibTeX RDF
2	Chuan Lin, Hai Zhou	Optimal wire retiming without binary search.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Jie-Hong Roland Jiang, Robert K. Brayton	Retiming and Resynthesis: A Complexity Perspective.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	James McCann, Nancy S. Pollard, S. Srinivasa	Physics-based motion retiming.	Symposium on Computer Animation	2006	DBLP DOI BibTeX RDF
2	Mongkol Ekpanyapong, Thaisiri Watewai, Sung Kyu Lim	Statistical Bellman-Ford algorithm with an application to retiming.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Cristian Soviani, Olivier Tardieu, Stephen A. Edwards	Optimizing sequential cycles through Shannon decomposition and retiming.	DATE	2006	DBLP DOI BibTeX RDF
2	Chuan Lin, Hai Zhou	Wire retiming as fixpoint computation.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Noureddine Chabini, Wayne Wolf	Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Jie-Hong Roland Jiang	On Some Transformation Invariants Under Retiming and Resynthesis.	TACAS	2005	DBLP DOI BibTeX RDF
2	Robert Fischer, Klaus Buchenrieder, Ulrich Nageldinger	Reducing the Power Consumption of FPGAs through Retiming.	ECBS	2005	DBLP DOI BibTeX RDF
2	Hai Zhou	Deriving a new efficient algorithm for min-period retiming.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Peter Suaris, Dongsheng Wang, Nan-Chi Chou	A practical cut-based physical retiming algorithm for field programmable gate arrays.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha	Optimizing Nested Loops with Iterational and Instructional Retiming.	EUC	2005	DBLP DOI BibTeX RDF
2	Miklós Bartha	Strong Retiming Equivalence of Synchronous Schemes.	CIAA	2005	DBLP DOI BibTeX RDF
2	Hsueh-Chih Yang, Lan-Rong Dung	On multiple-voltage high-level synthesis using algorithmic transformations.	ASP-DAC	2005	DBLP DOI BibTeX RDF	loop shrinking, multiple voltage scheduling, high-level synthesis, retiming, unfolding, low power circuit
2	Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria	Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	multiphase, sequential circuit, software pipelining, clock, Retiming
2	Ying Yi, Roger Woods, Lok-Kee Ting, C. F. N. Cowan	High Speed FPGA-Based Implementations of Delayed-LMS Filters.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	delayed LMS filters, retiming technique, hardware sharing, FPGA, adaptive filtering
2	Jason Cong, Sung Kyu Lim	Retiming-based timing analysis with an application to mincut-based global placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	Hai Zhou, Chuan Lin	Retiming for wire pipelining in system-on-chip.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	Noureddine Chabini, Wayne Wolf	Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Maher N. Mneimneh, Karem A. Sakallah, John Moondanos	Preserving synchronizing sequences of sequential circuits after retiming.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Chuan Lin, Hai Zhou	Wire Retiming for System-on-Chip by Fixpoint Computation.	DATE	2004	DBLP DOI BibTeX RDF
2	Chien-Hsun Tseng, Stuart Lawson	Full parallel process for multidimensional wave digital filtering via multidimensional retiming technique.	ISCAS	2004	DBLP DOI BibTeX RDF
2	Chuan Lin, Hai Zhou	Optimal wire retiming without binary search.	ICCAD	2004	DBLP DOI BibTeX RDF
2	Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	General loop fusion technique for nested loops considering timing and code size.	CASES	2004	DBLP DOI BibTeX RDF	embedded DSP, scheduling, retiming, code size, loop fusion
2	Dennis K. Y. Tong, Evangeline F. Y. Young	Performance-driven register insertion in placement.	ISPD	2004	DBLP DOI BibTeX RDF	post-retiming, register insertion, placement
2	Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.	Optimal joint module-selection and retiming with carry-save representation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Ingmar Neumann, Wolfgang Kunz	Layout driven retiming using the coupled edge timing model.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli	Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits.	SBCCI	2003	DBLP DOI BibTeX RDF
2	Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou	A physical retiming algorithm for field programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF
2	Ulrich Seidl, Klaus Eckl, Frank M. Johannes	Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information.	DATE	2003	DBLP DOI BibTeX RDF
2	Ruibing Lu, Cheng-Kok Koh	Interconnect Planning with Local Area Constrained Retiming.	DATE	2003	DBLP DOI BibTeX RDF
2	Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu	Retiming with Interconnect and Gate Delay.	ICCAD	2003	DBLP DOI BibTeX RDF
2	Chuan Lin, Hai Zhou	Retiming for Wire Pipelining in System-On-Chip.	ICCAD	2003	DBLP DOI BibTeX RDF
2	Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-Mean Sha	Design space minimization with timing and code size optimization for embedded DSP.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	retiming, unfolding, code size reduction, DSP processors
2	Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha	Code size reduction technique and implementation for software-pipelined DSP applications.	ACM Trans. Embedded Comput. Syst.	2003	DBLP DOI BibTeX RDF	scheduling, software pipelining, Retiming, DSP processors
2	Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman	Retiming and clock scheduling for digital circuit optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
2	Deshanand P. Singh, Stephen Dean Brown	Integrated retiming and placement for field programmable gate arrays.	FPGA	2002	DBLP DOI BibTeX RDF
2	P. Israsena, S. Summerfield	Bit-level retiming of high-speed digital recursive filters.	APCCAS	2002	DBLP DOI BibTeX RDF
2	Jason Cong	Timing closure based on physical hierarchy.	ISPD	2002	DBLP DOI BibTeX RDF	interconnect planning, logic hierarchy, physical hierarchy, retiming and pipelining, sequential arrival time, interconnect optimization, timing closure, multilevel optimization
2	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications. (PDF / PS)	ICPP	2002	DBLP DOI BibTeX RDF	Scheduling, Software pipelining, Retiming, DSP processors
2	Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge	Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.	ISSS	2002	DBLP DOI BibTeX RDF	rotation scheduling, software pipelining, retiming, unfolding
2	Alain Darte, Guillaume Huard	Complexity of Multi-dimensional Loop Alignment.	STACS	2002	DBLP DOI BibTeX RDF	Complexity, Program Transformation, Retiming, Automatic Parallelization, Loop Optimization