Search results for "routing area"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta	Partitioning Routing Area into Zones with Distinct Pins.	VLSI Design	2001	DBLP DOI BibTeX RDF
2	Aiguo Lu, Guenter Stenz, Frank M. Johannes	Technology Mapping for Minimizing Gate and Routing Area.	DATE	1998	DBLP DOI BibTeX RDF	Routing, Technology Mapping, Area Optimization
2	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
2	Jin-Tai Yan	A simple yet effective genetic approach for the orientation assignment on cell-based layout.	VLSI Design	1996	DBLP DOI BibTeX RDF	genetic approach, orientation assignment, cell-based layout, total wire length minimisation, placement phase, routing area reduction, orientation states, vertical orientation bit, horizontal orientation bit, genetic algorithms, VLSI, VLSI design, network routing, circuit layout CAD, integrated circuit layout
1	Qiang Gao, Yin Shen, Yici Cai, Hailong Yao	Analog circuit shielding routing algorithm based on net classification.	ISLPED	2010	DBLP DOI BibTeX RDF	analog routing, shielding routing, A* algorithm
1	Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi	A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong	Heuristic power/ground network and floorplan co-design method.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Fu-Wei Chen, Yi-Yu Liu	Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture.	DATE	2008	DBLP DOI BibTeX RDF
1	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig	Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures.	DSD	2008	DBLP DOI BibTeX RDF
1	Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig	Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures.	FCCM	2008	DBLP DOI BibTeX RDF
1	Bo Yang, Shigetoshi Nakatake, Hiroshi Murata	Fast Shape Optimization of Metallization Patterns for DMOS Based Driver.	ISQED	2008	DBLP DOI BibTeX RDF	Metallization pattern, Resistance, DMOS
1	Othman A. Al-Amoudi, Mohamed S. El-Azhari, Michael E. Woodward, Irfan Awan	Performance Analysis of Angle Routing in MANETs.	NBiS	2008	DBLP DOI BibTeX RDF
1	Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh	Block placement to ensure channel routability.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	routing space, placement, channel, routability
1	Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden	ISPD placement contest updates and ISPD 2007 global routing contest.	ISPD	2007	DBLP DOI BibTeX RDF
1	Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini	Reducing Interconnect Cost in NoC through Serialized Asynchronous Links.	NOCS	2007	DBLP DOI BibTeX RDF
1	Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi	Effective clustering technique to optimize routability of outer cluster nets.	FPGA	2006	DBLP DOI BibTeX RDF
1	Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang	Width and Timing-Constrained Wire Sizing for Critical Area Minimization.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee	Timing-constrained yield-driven wire sizing for critical area minimization.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Hsun-Chieh Yu, Rung-Bin Lin	Is more redundancy better for on-chip bus encoding.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis	Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Andy Ye, Jonathan Rose	Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Fabio Ricciato, René Pilz, Eduard Hasenleithner	Measurement-Based Optimization of a 3G Core Network: A Case Study.	NEW2AN	2006	DBLP DOI BibTeX RDF
1	Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He	A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Jinjun Xiong, Lei He	Probabilistic congestion model considering shielding for crosstalk reduction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Andy Gean Ye, Jonathan Rose	Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits.	FPGA	2005	DBLP DOI BibTeX RDF	datapath regularity, reconfigurable fabric, FPGA architecture, routing architecture, area efficiency
1	Liang Zhang, John Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon	Driver pre-emphasis techniques for on-chip global buses.	ISLPED	2005	DBLP DOI BibTeX RDF	current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus
1	Hao Yu, Lei He	Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction.	ISQED	2005	DBLP DOI BibTeX RDF
1	Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang	Spanning graph-based nonrectilinear steiner tree algorithms.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	T. Ozugur	Hierarchical provisioning for cellular networks.	IEEE Transactions on Wireless Communications	2005	DBLP DOI BibTeX RDF
1	Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang	Optimal planning for mesh-based power distribution.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng	A multiple level network approach for clock skew minimization with process variations.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Renqiu Huang, Ranga Vemuri	Analysis and evaluation of a hybrid interconnect structure for FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Jinjun Xiong, Lei He	Full-chip routing optimization with RLC crosstalk budgeting.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang	Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing.	SLIP	2003	DBLP DOI BibTeX RDF	?-geometry routing, ?-geometry-driven placement, wirelength reduction estimation
1	Shun-Ren Yang, Yi-Bing Lin	A Mobility Management Strategy for UMTS.	ICOIN	2003	DBLP DOI BibTeX RDF
1	Dongsheng Wang, Peter Suaris, Nan-Chi Chou	A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Amit Singh, Malgorzata Marek-Sadowska	Efficient circuit clustering for area and power reduction in FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF
1	Jinjun Xiong, Jun Chen, James Ma, Lei He	Post global routing RLC crosstalk budgeting.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham	Balancing the Interconnect Topology for Arrays of Processors between Cost and Power.	ICCD	2002	DBLP DOI BibTeX RDF
1	Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky	Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing.	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Po-Jen Chuang, Juei-Tang Chen, Yue-Tsuen Jiang	Balancing Buffer Utilization in Meshes Using a 'Restricted Area' Concept.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	Adaptive routing algorithms, balanced buffer utilization, performance evaluation, meshes, wormhole routing, virtual channels, turn model
1	Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh	RPack: routability-driven packing for cluster-based FPGAs.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	James D. Z. Ma, Lei He	Simultaneous signal and power routing under K model.	SLIP	2001	DBLP DOI BibTeX RDF	net ordering, on-chip inductance, shield insertion, interconnect estimation, interconnect design
1	Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez, Saeid Nooshabadi	A compact layout technique to minimize high frequency switching effects in high speed circuits.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez	A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits.	ISQED	2001	DBLP DOI BibTeX RDF
1	Jason Cong, Cheng-Kok Koh, Patrick H. Madden	Interconnect layout optimization under higher order RLC model forMCM designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Jaewon Oh, Massoud Pedram	Gated clock routing for low-power microprocessor design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Jun Dong Cho	Wiring space and length estimation in two-dimensional arrays.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen	A Performance-Driven I/O Pin Routing Algorithm.	ASP-DAC	1999	DBLP DOI BibTeX RDF
1	Young-Jun Cha, Chong S. Rim, Kazuo Nakajima	SEGRA: a very fast general area router for multichip modules.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Amir H. Salek, Jinan Lou, Massoud Pedram	An integrated logical and physical design flow for deep submicron circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Jaewon Oh, Massoud Pedram	Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
1	Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda	New FPGA Architecture for Bit-Serial Pipeline Datapath.	FCCM	1998	DBLP DOI BibTeX RDF
1	Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu	A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.	ITC	1998	DBLP DOI BibTeX RDF
1	Masahiro Nagamatu, Shakeel Ismail, Torao Yanaru	A continuous valued iterative algorithm for wire routing problems.	KES	1998	DBLP DOI BibTeX RDF
1	Hsiao-Feng Steven Chen, D. T. Lee	On crossing minimization problem.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Chau-Shen Chen, TingTing Hwang	Layout Driven Selection and Chaining of Partial Scan Flip-Flops.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	design for testability, matching, placement, global routing, partial scan, digital testing, layout optimization
1	Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo	Interconnect design for deep submicron ICs.	ICCAD	1997	DBLP DOI BibTeX RDF	required-arrival-time Steiner tree higher-order moment signal delay and integrity
1	Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska	Postlayout logic restructuring using alternative wires.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Venkat Thanvantri, Sartaj Sahni	Optimal folding of standard and custom cells.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	custom cell folding, standard cell folding, layout area
1	Tianxiong Xue, Ernest S. Kuh	Post routing performance optimization via multi-link insertion and non-uniform wiresizing.	ICCAD	1995	DBLP DOI BibTeX RDF	post routing performance optimization, link insertion and wiresizing, delay skew, routing area, delay
1	Yin Chan, Sun-Yuan Kung	Bit Level Block Matching Systolic Arrays.	ASAP	1995	DBLP DOI BibTeX RDF	bit level systolic array, video signal processing architecture, pipeline, block matching
1	Hirendu Vaishnav, Massoud Pedram	Logic extraction based on normalized netlengths. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	logic extraction, normalized netlengths, chip area, routing, logic design, logic synthesis, cost function, minimisation of switching nets
1	T. W. Her, Martin D. F. Wong	On over-the-cell channel routing with cell orientations consideration.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Masayuki Terai, Kazuo Nakajima, Kazuhiro Takahashi, Koji Sato	A new approach to over-the-cell channel routing with three layers.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Mohammad Hossain Heydari, Ioannis G. Tollis, Chunliang Xia	Algorithms and bounds for layer assignment of MCM routing.	IEEE Trans. VLSI Syst.	1994	DBLP DOI BibTeX RDF
1	Yang Cai, Martin D. F. Wong	On minimizing the number of L-shaped channels in building-block layout [VLSI].	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Steven T. Healey	An improved model for solving the optimal placement for river-routing problem.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Chung-Kuan Cheng, David N. Deutsch, Craig Shohara, Mark Taparauskas, Mark Bubien	Geometric compaction on channel routing.	IEEE Trans. on CAD of Integrated Circuits and Systems	1992	DBLP DOI BibTeX RDF
1	Yang Cai, Martin D. F. Wong	Channel/switchbox definition for VLSI building-block layout.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
1	Khe-Sing The, Martin D. F. Wong, Jason Cong	A layout modification approach to via minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
1	Pierre Abouzeid, K. Sakouti, Gabriele Saucier, Franck Poirot	Multilevel Synthesis Minimizing the Routing Factor.	DAC	1990	DBLP DOI BibTeX RDF
1	Yang Cai, D. F. Wong	A Channel/Switchbox Definition Algorithm for Building-Block Layout.	DAC	1990	DBLP DOI BibTeX RDF
1	Jer Min Jou, Jau-Yien Lee, Yachyang Sun, Jhing-Fa Wang	An Efficient VLSI Switch-Box Router.	IEEE Design & Test of Computers	1990	DBLP DOI BibTeX RDF
1	Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal	Serial Interfacing for Embedded-Memory Testing.	IEEE Design & Test of Computers	1990	DBLP DOI BibTeX RDF
1	Jason Cong, C. L. Liu	Over-the-cell channel routing.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
1	Christos A. Papachristou, Anil L. Pandya	A design scheme for PLA-based control tables with reduced area and time-delay cost.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
1	B. Lokanathan, Edwin Kinnen	Performance optimized floor planning by graph planarization.	DAC	1989	DBLP DOI BibTeX RDF
1	Khe-Sing The, D. F. Wong, Jason Cong	VIA Minimization by Layout Modification.	DAC	1989	DBLP DOI BibTeX RDF
1	Wayne Wei-Ming Dai	Hierarchical placement and floorplanning in BEAR.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
1	Shuo Huang, Omar Wing	Gate matrix partitioning.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
1	Chung-Kuan Cheng, David N. Deutsch	Improved Channel Routing by Via Minimization and Shifting.	DAC	1988	DBLP BibTeX RDF
1	Rostam Joobbani, Daniel P. Siewiorek	WEAVER: a knowledge-based routing expert.	DAC	1985	DBLP DOI BibTeX RDF	OPS5
1	Yoji Kajitani	Order of Channels for Safe Routing and Optimal Compaction of Routing Area.	IEEE Trans. on CAD of Integrated Circuits and Systems	1983	DBLP DOI BibTeX RDF
1	Maciej J. Ciesielski, Edwin Kinnen	An analytical method for compacting routing area in integrated circuits.	DAC	1982	DBLP DOI BibTeX RDF