Search results for "routing topologies"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Siew Cheong Au, Christopher Leckie, Ajeet Parhar, Gerard Wong	Efficient visualization of large routing topologies.	Int. Journal of Network Management	2004	DBLP DOI BibTeX RDF
2	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
2	Andrew B. Kahng, Kei Masuko, Sudhakar Muddu	Analytical delay models for VLSI interconnects under ramp input.	ICCAD	1996	DBLP DOI BibTeX RDF	SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections
1	Ning Wang, Kin-Hon Ho, George Pavlou	AMPLE: an adaptive traffic engineering system based on virtual routing topologies.	IEEE Communications Magazine	2012	DBLP DOI BibTeX RDF
1	Phoebus Chen, Karl Henrik Johansson, Paul Balister, Béla Bollobás, Shankar Sastry	Multi-path Routing Metrics for Reliable Wireless Mesh Routing Topologies	CoRR	2011	DBLP BibTeX RDF
1	Christian Henke, Robert Wuttke, Tanja Zseby, Konrad Campowsky	On Creating Overlay Routing Topologies between Heterogeneous Experimental Facilities.	TRIDENTCOM	2011	DBLP DOI BibTeX RDF
1	Damiano Varagnolo, Phoebus Chen, Luca Schenato, Shankar S. Sastry	Performance analysis of different routing protocols in Wireless Sensor Networks for real-time estimation.	CDC	2008	DBLP DOI BibTeX RDF
1	Ning Wang, Kin-Hon Ho, George Pavlou	Adaptive Multi-topology IGP Based Traffic Engineering with Near-Optimal Network Performance.	Networking	2008	DBLP DOI BibTeX RDF
1	Ricardo S. Ferreira, Alisson Garcia, Tiago Teixeira, João M. P. Cardoso	A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Ariel Orda, Ben-Ami Yassour	Maximum-lifetime routing algorithms for networks with omnidirectional and directional antennas.	MobiHoc	2005	DBLP DOI BibTeX RDF	routing, wireless networks, multicast, broadcast, lifetime, unicast
1	Chanseok Hwang, Massoud Pedram	Interconnect design methods for memory design.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Jacob R. Minz, Sung Kyu Lim	Layer assignment for reliable system-on-package.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Liang Zhang, Wentai Liu, Rizwan Bashirullah, John Wilson, Paul D. Franzon	Simplified delay design guidelines for on-chip global interconnects.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	effective attenuation constant, first incident switching, lossy transmission line, delay, global interconnects, RLC
1	Gurmeet Singh Manku	Balanced binary trees for ID management and load balance in distributed hash tables.	PODC	2004	DBLP DOI BibTeX RDF	ID management, peer to peer, load balance, P2P, DHT, distributed hash table, binary tree
1	Gurmeet Singh Manku	Routing networks for distributed hash tables.	PODC	2003	DBLP DOI BibTeX RDF
1	Craig A. Lee, Eric Coe, Cauligi S. Raghavendra, J. Matt Clark, James Stepanek, Sameer Bhatia, Rohan Puri	Scalable Time Management Algorithms using Active Networks for Distributed Simulation.	DANCE	2002	DBLP DOI BibTeX RDF	distributed simulation, HLA, Active networks, time management
1	K. K. Lee, D. F. Wong	LRoute: a delay minimal router for hierarchical CPLDs.	FPGA	2001	DBLP DOI BibTeX RDF	complex programmable logic devices, routing, hierarchical model, Lagrangian relaxation
1	Craig A. Lee, Eric Coe, J. Matt Clark, James Stepanek, Kirstie L. Bellman, Cauligi S. Raghavendra	Time Management in Active Networks.	Active Middleware Services	2001	DBLP DOI BibTeX RDF
1	Jason Cong, Cheng-Kok Koh, Patrick H. Madden	Interconnect layout optimization under higher order RLC model forMCM designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Sushil Chandra Jain, Anshul Kumar, Shashi Kumar	Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.	FPL	2000	DBLP DOI BibTeX RDF
1	Scott Hauck, Gaetano Borriello, Carl Ebeling	Mesh routing topologies for multi-FPGA systems.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Avishai Mandelbaum, William A. Massey, Martin I. Reiman	Strong approximations for Markovian service networks.	Queueing Syst.	1998	DBLP DOI BibTeX RDF	strong approximations, fluid approximations, queues with abandonment, queues with retrials, nonstationary queues, queueing networks, priority queues, diffusion approximations, Jackson networks, multiserver queues
1	Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo	Interconnect design for deep submicron ICs.	ICCAD	1997	DBLP DOI BibTeX RDF	required-arrival-time Steiner tree higher-order moment signal delay and integrity
1	Andrew B. Kahng, Sudhakar Muddu	An analytical delay model for RLC interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Joe G. Xi, Wayne Wei-Ming Dai	Jitter-tolerant clock routing in two-phase synchronous systems.	ICCAD	1996	DBLP DOI BibTeX RDF	Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew
1	Bernard A. McCoy, Gabriel Robins	Non-tree routing [VLSI layout].	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Scott Hauck, Gaetano Borriello, Carl Ebeling	Mesh Routing Topologies for Multi-FPGA Systems.	ICCD	1994	DBLP BibTeX RDF
1	Kai-Yuan Chao, D. F. Wong	Layer assignment for high-performance multi-chip modules.	ICCAD	1994	DBLP DOI BibTeX RDF