Search results for "scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
7	Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Scan insertion criteria for low design impact.	VTS	1996	DBLP DOI BibTeX RDF	scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
7	Kwang-Ting Cheng	Partial scan designs without using a separate scan clock.	VTS	1995	DBLP DOI BibTeX RDF	flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock
6	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen	Peak-power reduction for multiple-scan circuits during test application.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
6	Irith Pomeranz, Sudhakar M. Reddy	Reducing test application time for full scan circuits by the addition of transfer sequences.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits
6	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
6	Hao Zheng, Kewal K. Saluja, Rajiv Jain	Test application time reduction for scan based sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time
6	Sridhar Narayanan, Melvin A. Breuer	Asynchronous multiple scan chain.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous multiple scan chains, scan flip-flops, control complexity, I/O pin count, DFT method, logic IC, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, flip-flops, integrated logic circuits, scan designs, boundary scan testing, test application time
5	Seongmoon Wang, Wenlong Wei	A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture.	ASP-DAC	2007	DBLP DOI BibTeX RDF	peak current reduction, average power dissipation, clock tree construction, special scan cells, scan chain reordering, ATPG, scan designs
5	Malav Shah	Efficient scan-based BIST scheme for low power testing of VLSI chips.	ISLPED	2006	DBLP DOI BibTeX RDF	test-per-clock, test-per-scan, scan, partial scan, switching activity, test length
5	Gundolf Kiefer, Hans-Joachim Wunderlich	Deterministic BIST with Multiple Scan Chains.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	deterministic scan-based BIST, multiple scan paths, parallel scan
5	Gundolf Kiefer, Hans-Joachim Wunderlich	Deterministic BIST with multiple scan chains.	ITC	1998	DBLP DOI BibTeX RDF	deterministic scan-based BIST, multiple scan paths, parallel scan
5	Kee Sup Kim, Charles R. Kime	Partial scan flip-flop selection by use of empirical testability.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	scan flip-flop selection, serial scan, design for testability, testability, partial scan
5	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partial scan design and test sequence generation based on reduced scan shift method.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	partial scan circuit, short test sequence, reduced scan shift, scan design, test sequence generation
5	Seiken Yano	Unified scan design with scannable memory arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits
5	Samantha Edirisooriya, Geetani Edirisooriya	Diagnosis of scan path failures.	VTS	1995	DBLP DOI BibTeX RDF	scan path failures, scan based diagnostic schemes, faulty circuits, logic circuitry, scan chain fault diagnosis, fault diagnosis, logic testing, integrated circuit testing, design for testability, combinational circuits, integrated logic circuits
4	Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	Efficient partial scan cell gating for low-power scan-based testing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	partial gating, scan cell gating, Low-power testing, scan-based testing
4	Massimo Bilancia, Silvestro Montrone, Paola Perchinunno	A Model-Based Scan Statistics for Detecting Geographical Clustering of Disease.	ICCSA	2009	DBLP DOI BibTeX RDF	Disease clustering, Model-based scan statistics, BYM model, Lung cancer mortality, Spatial scan statistics
4	Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li	Layout-aware scan chain reorder for launch-off-shift transition test coverage.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	scan chain ordering, test generation, transition faults, Scan test
4	Xijiang Lin, Yu Huang 0005	Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Scan shift, Low power test, Scan test, Signal probability
4	Ozgur Sinanoglu	Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Combinational decompressors, Scan cell partitioning, Test data compression, Scan-based testing
4	Ozgur Sinanoglu	Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing
4	Yong-sheng Cheng, Zhiqiang You, Jishun Kuang	Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction.	DELTA	2008	DBLP DOI BibTeX RDF	full scan testing, scan tree, routing complexity, test response data volume, design-for-testability
4	King Leong Lee, Nadir Z. Basturkmen, Srikanth Venkataraman	Diagnosis of Scan Clock Failures.	VTS	2008	DBLP DOI BibTeX RDF	scan clock, diagnosis, scan chain
4	Elif Alpaslan, Yu Huang 0005, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak	Reducing Scan Shift Power at RTL.	VTS	2008	DBLP DOI BibTeX RDF	Test Power Reduction, Power-Sensitive Scan Cell, RTL DFT, Timing Closure, Scan Based Test
4	Yuri Dotsenko, Naga K. Govindaraju, Peter-Pike J. Sloan, Charles Boyd, John Manferdelli	Fast scan algorithms on graphics processors.	ICS	2008	DBLP DOI BibTeX RDF	all-prefix-sum, segmented scan, parallel algorithm, GPU, GPGPU, scan, HPC, many-core
4	Dong Xiang, Mingjing Chen, Hideo Fujiwara	Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Random testability, scan enable signal, weighted random testing, scan-based BIST
4	Young-Ho Choi, Se-Young Oh	Map building through pseudo dense scan matching using visual sonar data.	Auton. Robots	2007	DBLP DOI BibTeX RDF	Robust visual sonar, Pseudo dense scan, Adaptive scan matching, Trajectory correction
4	Ozgur Sinanoglu	Low Cost Scan Test by Test Correlation Utilization.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	test correlation, scan architecture design, test data compression, scan-based testing
4	Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	Scan-Based Tests with Low Switching Activity.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	scan shift, test response capture, supply current, power dissipation, switching activity, scan-based test
4	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda	Systematic Scan Reconfiguration.	ASP-DAC	2007	DBLP DOI BibTeX RDF	systematic scan reconfiguration, test data compression technique, single-stuck fault test sets, transition fault test sets, scan chains
4	Deepak Agarwal, Andrew McGregor, Jeff M. Phillips, Suresh Venkatasubramanian, Zhengyuan Zhu	Spatial scan statistics: approximations and performance study.	KDD	2006	DBLP DOI BibTeX RDF	Kulldorff scan statistic, discrepancy, spatial scan statistics
4	J. Treurniet	Detecting low-profile scans in TCP anomaly event data.	PST	2006	DBLP DOI BibTeX RDF	distributed scan detection, scan detection, slow scan detection, network security, TCP, anomaly detection
4	Mehrdad Nourani, Mohammad H. Tehranipour	RL-huffman encoding for test compression and power reduction in scan applications.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Huffman encoding, scan applications, scan-in test power, test pattern compression, power reduction, switching activities, test compression, Compression ratio, run-length encoding, decompression
4	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Power-Driven Routing-Constrained Scan Chain Design.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	scan chain design, DfT, low power testing, scan testing
4	Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu	Reducing Average and Peak Test Power Through Scan Chain Modification.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	test power reduction, scan chain modification, average test power, peak test power, scan testing
4	Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier	Enhanced Reduced Pin-Count Test for Full-Scan Design.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	reduced pin-count test, core test, design for testability, ATE, boundary-scan test, scan test
4	Kuen-Jong Lee, Tsung-Chu Huang	An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	multiple scan chains, interleaving scan, test power reduction, peak power reduction
4	Bruce S. Greene, Samiha Mourad	Partial Scan Testing on the Register-Transfer Level.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	RT-level, fault coverage, partial scan, scan design, graph reduction
4	Gundolf Kiefer, Hans-Joachim Wunderlich	Deterministic BIST with Partial Scan.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	deterministic scan-based BIST, partial scan
4	Abhijit Jas, Bahram Pouya, Nur A. Touba	Virtual Scan Chains: A Means for Reducing Scan Length in Cores.	VTS	2000	DBLP DOI BibTeX RDF	Compression/Decompression, Virtual Scan, Built-In Self-Test, Mapping, Design-for-Testability, LFSR, System Integrator, Integrated Circuits, Integrated Circuits, Scan Chains, Embedded Cores, Digital Testing, Reseeding
4	Janusz Rajski, Jerzy Tyszer, Nadime Zacharia	Test Data Decompression for Multiple Scan Designs with Boundary Scan.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	reseeding of LFSRs, multiple scan chains, test data decompression, built-in self-test, design for testability, Boundary scan, scan-based designs
4	Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee	Functional Scan Chain Testing.	DATE	1998	DBLP DOI BibTeX RDF	functional scan chain, alternating sequence, scan chain testing, design for testability, test point insertion
4	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe	Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique.	DATE	1998	DBLP DOI BibTeX RDF	Scan chain selection, RT and gate levels, Partial scan, Synthesis for testability
4	Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara	An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	synchronizable finite state machines, sequential circuits synthesis, extended synchronizing sequence, scan inputs, normal inputs, MCNC'91 benchmark FSM, minimum-length extended synchronizing sequence, test generation, finite state machines, DFT, heuristic algorithm, minimization, partial scan, synthesis for testability, state assignment, state transition, state encoding
4	Subhrajit Bhattacharya, Sujit Dey	H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.	VTS	1996	DBLP DOI BibTeX RDF	H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
4	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
4	Roberto Bevacqua, Luca Guerrazzi, Franco Fummi	SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation.	EUROMICRO	1996	DBLP DOI BibTeX RDF	test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
4	Rajesh Gupta, Melvin A. Breuer	Partial scan design of register-transfer level circuits.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	serial scan design, I-paths, design for testability, register-transfer level designs, balanced structures, partial scan design
4	Johannes Steensma, Francky Catthoor, Hugo De Man	Partial scan and symbolic test at the register-transfer level.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	data path test, partial scan selection, symbolic test pattern generation, partial scan application schemes
4	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
4	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, transformation, timing, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
4	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
4	Hardy J. Pottinger, Chien-Yuh Lin	Using a reconfigurable field programmable gate array to demonstrate boundary scan with built in self test.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	student experiments, educational aids, reconfigurable FPGA, XC4000 Logic Cell Array Family, IEEE Standard 1149.1, XC4003PC84-6, field programmable gate arrays, field programmable gate array, logic testing, built-in self test, built-in self-test, computer science education, integrated circuit testing, design for testability, logic design, BIST, teaching, fault simulation, integrated circuit design, boundary scan, demonstration, boundary scan testing, Xilinx, electronic engineering education
4	Ajay Khoche, Erik Brunvand	Testing self-timed circuits using partial scan.	ASYNC	1995	DBLP DOI BibTeX RDF	sequential network, partial scan environment, logic testing, sequential circuits, asynchronous circuits, partial scan, data paths, self-timed circuits
4	Ajay Khoche, Erik Brunvand	A partial scan methodology for testing self-timed circuits.	VTS	1995	DBLP DOI BibTeX RDF	partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits
4	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
4	Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel	Cyclic stress tests for full scan circuits.	VTS	1995	DBLP DOI BibTeX RDF	cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits
4	Bapiraju Vinnakota, Nicholas J. Stessman	Reducing test application time in scan design schemes.	VTS	1995	DBLP DOI BibTeX RDF	scan design schemes, computationally intractable problem, test vector correlation, graph theory, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic testing, fault simulation, fault coverage, correlation methods, boundary scan testing, test times, test application time, heuristic techniques
4	Arun Balakrishnan, Srimat T. Chakradhar	Partial scan design for technology mapped circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design
4	Elizabeth M. Rudnick, Janak H. Patel	A genetic approach to test application time reduction for full scan and partial scan circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits
4	Jacob Savir	Module level weighted random patterns.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
4	Thomas A. Ziaja, Earl E. Swartzlander Jr.	Boundary scan in board manufacturing.	J. Electronic Testing	1994	DBLP DOI BibTeX RDF	Board and system test, boundary scan description language, design-for-test, boundary scan
4	Prab Varma, Tushar Gheewala	The economics of scan-path design for testability.	J. Electronic Testing	1994	DBLP DOI BibTeX RDF	state retention problem, Design for testability, scan, partial scan, test economics, life-cycle costs
4	Nazar S. Haider, Nick Kanopoulos	Efficient board interconnect testing using the split boundary scan register.	J. Electronic Testing	1993	DBLP DOI BibTeX RDF	IEEE std. 1149.1-1990, split boundary scan register, BIST, boundary scan
4	Bulent I. Dervisoglu	Features of a Scan and Clock Resource chip for providing access to board-level test functions.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	diagnostics bus, design-for-testability, scan, boundary scan, pseudorandom testing
4	Matthew L. Fichtenbaum, Gordon D. Robinson	Scan test architectures for digital board testers.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	tester architecture, scan, boundary scan
4	Thomas W. Williams, Kenneth P. Parker	Design for Testability - A Survey.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	Built-In Logic Block Observation (BILBO), Level Sensitive Scan Design (LSSD), Random Access Scan, Scan/Set Logic, testing, test generation, self test, Signature Analysis, Scan Path
3	Lei Shi, Vandana Pursnani Janeja	Anomalous Window Discovery for Linear Intersecting Paths.	IEEE Trans. Knowl. Data Eng.	2011	DBLP DOI BibTeX RDF	spatial scan window, linear scan statistic, anomaly detection, Spatial scan statistics
3	Christian Wimmer, Michael Franz	Linear scan register allocation on SSA form.	CGO	2010	DBLP DOI BibTeX RDF	SSA form deconstruction, lifetime analysis, linear scan, Java, register allocation, just-in-time compilation, SSA form
3	Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara	Graph theoretic approach for scan cell reordering to minimize peak shift power.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power droop, scan chain reordering, peak power
3	Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas	Gating internal nodes to reduce power during scan shift.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	gating internal nodes, scan shift power reduction, low power test
3	Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie	Scan-chain design and optimization for three-dimensional integrated circuits.	JETC	2009	DBLP DOI BibTeX RDF	scan-chain design, genetic algorithm, integer linear programming, randomized rounding, LP relaxation, 3D ICs
3	Antoni Burguera, Yolanda González Cid, Gabriel Oliver	On the use of likelihood fields to perform sonar scan matching localization.	Auton. Robots	2009	DBLP DOI BibTeX RDF	Likelihood fields, Sonar, Scan matching
3	Zhen Chen, Dong Xiang, Boxue Yin	A power-effective scan architecture using scan flip-flops clustering and post-generation filling.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
3	Khadija Houerbi Ramah, Kavé Salamatian, Farouk Kamoun	Scan Surveillance in Internet Networks.	Networking	2009	DBLP DOI BibTeX RDF	scan monitoring, Networks, anomaly detection, Information Theory
3	David Sandberg, Krister Wolff, Mattias Wahde	A Robot Localization Method Based on Laser Scan Matching.	FIRA RoboWorld Congress	2009	DBLP DOI BibTeX RDF	laser scan matching, robot pose estimation, Robot localization
3	Maciej Nikodem	Boundary Scan Security Enhancements for a Cryptographic Hardware.	EUROCAST	2009	DBLP DOI BibTeX RDF	IEEE 1149, side-channel attacks, countermeasures, boundary scan
3	Lifeng He, Yuyan Chao, Kenji Suzuki, Hidenori Itoh	A Run-Based One-Scan Labeling Algorithm.	ICIAR	2009	DBLP DOI BibTeX RDF	label equivalence, raster scan, connected component, run-length encoding, Labeling algorithm
3	Lei Shi, Vandana Pursnani Janeja	Anomalous window discovery through scan statistics for linear intersecting paths (SSLIP).	KDD	2009	DBLP DOI BibTeX RDF	anomalous window discovery, intersecting paths, scan statistic, traffic accidents
3	Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang	A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	profiling, design for testability, Diagnosis, fault, scan chain
3	Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi	A Selective Trigger Scan Architecture for VLSI Testing.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power
3	Dong Xiang, Mingjing Chen, Jia-Guang Sun	Scan BIST with biased scan test signals.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	random testability, test signal, biased random testing, scan-based BIST
3	Tsung-Ching Huang, Kwang-Ting (Tim) Cheng, Huai-Yuan Tseng, Chen-Pang Kung	Reliability analysis for flexible electronics: Case study of integrated a-Si: H TFT scan driver.	JETC	2008	DBLP DOI BibTeX RDF	amorphous hydrogenated silicon (a-Si:H), flexible electronics, scan driver, thin-film transistor, Reliability, threshold voltage
3	Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	DfT, Scan, Test data compression, Low power testing
3	Ho Fai Ko, Nicola Nicolici	Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Skewed-load, Scan division, At-speed test, Low-power test
3	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	At-speed scan testing, Capture switching activity, X-filling, Test cube, ATPG, Low power testing
3	Hong-Sik Kim, Sungho Kang, Michael S. Hsiao	A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Keyword System on a chip, Test compression, Low power testing, Scan testing
3	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Scan Test Response Compaction Combined with Diagnosis Capabilities.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE
3	Rohit Kapur, Subhasish Mitra, Thomas W. Williams	Historical Perspective on Scan Compression.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	scan compression, test data volume reduction, IC testing, test application time reduction
3	Chao-Wen Tzeng, Shi-Yu Huang	UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	multicasting, broadcasting, DFT, test compression, scan test
3	Anshuman Chandra, Rohit Kapur	Interval Based X-Masking for Scan Compression Architectures.	ISQED	2008	DBLP DOI BibTeX RDF	X masking, test, compression, DFT, scan
3	Fei Wang, Yu Hu, Xiaowei Li	Adaptive Diagnostic Pattern Generation for Scan Chains.	DELTA	2008	DBLP DOI BibTeX RDF	very large scale integration (VLSI), testing, diagnosis, Boolean satisfiability, scan chain
3	Matthew K. Feusner, Brian Lukoff	Testing for statistically significant differences between groups of scan patterns.	ETRA	2008	DBLP DOI BibTeX RDF	scan pattern, similarity test, eye tracking, analysis, statistics, comparison, sequence comparison, scanpath
3	Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding	Scan chain clustering for test power reduction.	DAC	2008	DBLP DOI BibTeX RDF	test, low power, design for test, scan design
3	Liangliang Yang, Yunfei Zhou, Haihong Pan, Wei Teng	Realization of the Synchronization Mechanism of Step and Scan Projection Lithography.	ICIRA	2008	DBLP DOI BibTeX RDF	Step and scan projection lithography, state synchronization, high speed high precision motion control, synchronization control
3	Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	On the Detectability of Scan Chain Internal Faults An Industrial Case Study.	VTS	2008	DBLP DOI BibTeX RDF	Faults in scan cells, stuck-at and stuck-on faults
3	Anshuman Chandra, Rohit Kapur	Bounded Adjacent Fill for Low Capture Power Scan Testing.	VTS	2008	DBLP DOI BibTeX RDF	capture power, random fill, shift power, test, low power, scan
3	Sunghoon Chun, Taejin Kim, YongJoon Kim, Sungho Kang	An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation.	VTS	2008	DBLP DOI BibTeX RDF	Scan chain based test, Diagnosis, Symbolic Simulation
3	Yu-Ze Wu, Mango Chia-Tso Chao	Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes.	VTS	2008	DBLP DOI BibTeX RDF	signal transitions, correlation, reordering, scan-chain
3	Daofang Cheng, Xiaolong Li, Wenfa Qi, Bin Yang	A Statistics-Based Watermarking Scheme Robust to Print-and-Scan.	ISECS	2008	DBLP DOI BibTeX RDF	print-and-scan, distribution, DCT, digital watermarking