Search results for "self-biased"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Leila Koushaeian, Stan Skafidas	A 65nm CMOS low-power, low-voltage bandgapreference with using self-biased composite cascode opamp.	ISLPED	2010	DBLP DOI BibTeX RDF	bandgap voltage reference, self-biased, self-cascode, temperature coefficient, voltage reference
3	John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas	Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL.	DAC	2003	DBLP DOI BibTeX RDF	adaptive bandwidth, clock multiplication, frequency synthesis, self biased, analog circuits, PLL, phase-locked loop, clock generation
2	Linga Reddy Cenkeramaddi, Tajeshwar Singh, Trond Ytterdal	Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	CMUT-CMOS, analog front-end for CMUTs, charge sampling, sampling, CSA
2	Francisco Serra-Graells, Josep Maria Margarit, Lluís Terés	A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS Imagers.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Jennifer Blain Christen, Andreas G. Andreou	A Self-Biased Operational Transconductance Amplifier in 0.18 micron 3D SOI-CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Sandeep Patil, Michael Wieckowski, Martin Margala	A Self-Biased Charge-Transfer Sense Amplifier.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Yat-Hei Lam, Suet-Chui Koon, Wing-Hung Ki, Chi-Ying Tsui	Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Edgar Mauricio Camacho-Galeano, Carlos Galup-Montoro, Márcio C. Schneider	An ultra-low-power self-biased current reference.	SBCCI	2004	DBLP DOI BibTeX RDF	inversion level, self-cascode MOSFET, design methodology, low-voltage, ultra-low-power, current reference
2	Pradip Mandal, V. Visvanathan	A Self-Biased High Performance Folded Cascode CMOS Op-Amp.	VLSI Design	1997	DBLP DOI BibTeX RDF
1	Roger Figueras, Justo Sabadell, Lluís Terés, Francesc Serra-Graells	A 70-mu m Pitch 8-mu W Self-Biased Charge-Integration Active Pixel for Digital Mammography.	IEEE Trans. Biomed. Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Michael Figueiredo, Rui Santos-Tavares, Edinei Santin, João Ferreira, Guiomar Evans, João Goes	A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Le Wang, Luke Theogarajan	An 18µW 79dB-DR 20KHz-BW MASH ΔΣ modulator utilizing self-biased amplifiers for biomedical applications.	CICC	2011	DBLP DOI BibTeX RDF
1	Josep Maria Margarit, Michele Dei, Lluís Terés, Francisco Serra-Graells	A self-biased PLL-tuned AER pixel for high-speed infrared imagers.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Davide Marano, Gaetano Palumbo, Salvatore Pennisi	Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Yat-Hei Lam, Wing-Hung Ki	CMOS Bandgap References With Self-Biased Symmetrically Matched Current-Voltage Mirror and Extension of Sub-1-V Design.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	José Rui Custódio, Michael Figueiredo, Edinei Santin, João Goes	A CMOS Inverter-Based Self-biased Fully Differential Amplifier.	DoCEIS	2010	DBLP DOI BibTeX RDF
1	David E. Duarte, Suching Hsu, Keng L. Wong, Mingwei Huang, Greg Taylor	Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
1	Le Wang, Luke Theogarajan	A micropower delta-sigma modulator based on a self-biased super inverter for neural recording systems.	CICC	2010	DBLP DOI BibTeX RDF
1	Biju Viswanathan, Vijay Viswam, R. Kulanthaivelu, Joseph J. Vettickatt, S. R. Ramya Nair, Lekshmi S. Chandran	4 GHz 130nm Low Voltage PLL Based on Self Biased Technique.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Michael Figueiredo, Edinei Santin, João Goes, Rui Santos-Tavares, Guiomar Evans	Two-stage fully-differential inverter-based self-biased CMOS amplifier with high efficiency.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Edinei Santin, Michael Figueiredo, Rui Tavares, João Goes, Luís B. Oliveira	Fast-settling low-power two-stage self-biased CMOS amplifier using feedforward-regulated cascode devices.	ICECS	2010	DBLP DOI BibTeX RDF
1	Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan	Self-Biased Unity-Gain Buffers With Low Gain Error.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Michael Figueiredo, Tomasz Michalak, João Goes, Luís Gomes, Pawel Sniatala	Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits.	ICECS	2009	DBLP DOI BibTeX RDF
1	G. A. V. Sai Praneeth, Anil K. Saini	A self biased operational amplifier at ultra low power supply voltage.	ICECS	2009	DBLP DOI BibTeX RDF
1	Matías R. Miguez, Alfredo Arnaud, Joel Gak	A self-protected integrated switch in a HV technology.	SBCCI	2009	DBLP DOI BibTeX RDF	design, drivers
1	M. J. Uddin, Muhammad I. Ibrahimy, M. A. Hasan, Mohd. Alauddin Mohd. Ali, Mamun Bin Ibne Reaz	CMOS 2.45GHz RF power amplifier for RFID reader.	SBCCI	2009	DBLP DOI BibTeX RDF	power splitter, transponder, RFID
1	Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar	A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Edgar Mauricio Camacho-Galeano, Juliano Q. Moreira, Maicon D. Pereira, Adilson J. Cardoso, Carlos Galup-Montoro, Márcio C. Schneider	Temperature performance of sub-1V ultra-low power current sources.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Josep Maria Margarit, Lluís Terés, Francisco Serra-Graells	A Sub-µW fully programmable CMOS DPS for uncooled infrared fast imaging.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Yiling Zhang, Valencia M. Joyner, Ruida Yun, Sameer R. Sonkusale	A 700Mbit/s CMOS capacitive feedback front-end amplifier with automatic gain control for broadband optical wireless links.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Vijay Khawshe, Pravin V. Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara, Manish Jain, Navin K. Mishra, Abhijit Abhyankar	A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Sang-Min Han, Ji-Yong Park, Tatsuo Itoh	A Self-Biased Receiver System Using the Active Integrated Antenna.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Franz Schlögl, Horst Dietrich, Horst Zimmermann	Differential OPAMP with Inherent Common-Mode Control and Self-Biased Cascodes in 120nm CMOS.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Jiefeng Yan, Lei Xie, Xiaoyang Zeng, Tingao Tang	Adaptive bandwidth PLL with compact current mode filter.	ISCAS	2006	DBLP DOI BibTeX RDF
1	B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni	Application of Alpha Power Law Models to PLL Design Methodology.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	U. Cilingiroglu, Siew Kuok Hoon	An optimally self-biased threshold-voltage extractor [MOSFET circuit parametric testing].	IEEE T. Instrumentation and Measurement	2003	DBLP DOI BibTeX RDF
1	Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Jaewoo Kyung, Gwanghyeon Baek, Chun-An Lee, Jong Duk Lee, Byung-Gook Park	Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic. (PDF / PS)	ISMVL	2003	DBLP DOI BibTeX RDF
1	Z. Q. Li, X. W. Sun, W. Fan, G. J. Qi	Bias-adaptive cross-coupled CMOS MAGFET pair for bipolar magnetic field detection.	ISCAS	2003	DBLP DOI BibTeX RDF
1	R. M. Fox, M. Nagarajan	Multiple operating points in a CMOS log-domain filter.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Chisato Numaoka	Innate Sociability: Self-Biased Conditioning.	Applied Artificial Intelligence	1998	DBLP DOI BibTeX RDF