Search results for "sequential circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Debesh K. Das, Bhargab B. Bhattacharya	Testable design of non-scan sequential circuits using extra logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
5	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez	Diagnostic of path and gate delay faults in non-scan sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults
4	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita	Test sequence compaction for sequential circuits with reset states.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
4	Michiko Inoue, Emil Gizdarski, Hideo Fujiwara	A class of sequential circuits with combinational test generation complexity under single-fault assumption.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
4	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
4	Michele Favalli, Cecilia Metra	Low-level error recovery mechanism for self-checking sequential circuits. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	low-level error recovery mechanism, self-checking sequential circuits, reliability requirements, small embedded systems, sequential circuits, design methodology, transient faults, delay faults, fault tolerant capabilities, crosstalk faults
4	Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler	Deriving Signal Constraints to Accelerate Sequential Test Generation.	VLSI Design	1997	DBLP DOI BibTeX RDF	sequential test generation algorithm acceleration, signal constraints, large sequential circuits, deterministic sequential test generation, signal constraint computation technique, line probabilities, line justification techniques, benchmark sequential circuits, test generation time reduction, production sequential circuits, 3-valued signal probabilities, fault diagnosis, fault coverage, symbolic simulation, truth table
4	Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya	Isomorph-redundancy in sequential circuits.	VTS	1996	DBLP DOI BibTeX RDF	isomorph-redundancy, reduced sequential machine, infinite family, VLSI, logic testing, redundancy, integrated circuit testing, design for testability, logic design, sequential circuits, sequential circuits, DFT, state diagram
4	Jalal A. Wehbeh, Daniel G. Saab	Initialization of sequential circuits and its application to ATPG.	VTS	1996	DBLP DOI BibTeX RDF	initialization sequence, X-value simulation, functional initializability, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, ATPG, automatic testing, integrated logic circuits, structural decomposition
4	Yuan Lu, Irith Pomeranz	Synchronization of large sequential circuits by partial reset.	VTS	1996	DBLP DOI BibTeX RDF	large synchronous sequential circuits, synchronization, sequential circuits, synchronisation, feedback loops, synchronizing sequence, partial reset
4	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical path delay fault coverage estimation for synchronous sequential circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
4	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
4	Shiyi Xu, Gercy P. Dias	Testability forecasting for sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testability forecasting, transitive closure algorithm, number of test patterns, computational complexity, fault diagnosis, logic testing, logic testing, statistical analysis, design for testability, sequential circuits, sequential circuits, logic CAD, fault coverage, regression models, automatic test software, CPU time, test generation algorithms
4	S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault	Test configurations to enhance the testability of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
4	Stanley Habib, Quan Xu	Technology mapping algorithms for sequential circuits using look-up table based FPGAS.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table
4	Hao Zheng, Kewal K. Saluja, Rajiv Jain	Test application time reduction for scan based sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time
4	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
4	Albrecht P. Stroele	Signature analysis and aliasing for sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	built-in self-test techniques, test registers, subcircuits, irreducible characteristic polynomial, limiting value, fault diagnosis, logic testing, built-in self test, integrated circuit testing, sequential circuits, sequential circuits, aliasing, signature analysis, shift registers, test lengths
4	Víctor H. Champac, Joan Figueras	Testability of floating gate defects in sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
4	Rajesh Nair, Dong Sam Ha	VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	parallel pattern fault simulator, VLSI, VLSI, fault diagnosis, heuristics, logic testing, integrated circuit testing, sequential circuits, digital simulation, VISION, circuit analysis computing, flip-flops, synchronous sequential circuits, benchmark circuits
4	Samir Lejmi, Bozena Kaminska, Bechir Ayari	Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudo-exhaustive testing
4	Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal	Functional test generation for non-scan sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, functional test vectors, growth and disappearance fault model, complete stuck fault coverage, algebraic transformations, synthesized FSMs, VLSI, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, automatic testing, functional test generation
4	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
4	Hiroshi Date, Michinobu Nakao, Kazumi Hatayama	A parallel sequential test generation system DESCARTES based on real-valued logic simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	parallel sequential test generation system, DESCARTES, real-valued logic simulation, redundant fault identification program, algorithmic test generation program, ISCAS '89 benchmark sequential circuits, distributed processing environment oriented system, concurrent accelerative test generation, parallel algorithms, computational complexity, VLSI, fault diagnosis, logic testing, redundancy, design for testability, sequential circuits, logic CAD, VLSI design, stuck-at faults, automatic test generation, synchronous sequential circuits, automatic test software, test quality
3	Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan	A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	sequential circuits, Dynamic Bayesian networks, TDM
3	Irith Pomeranz, Sudhakar M. Reddy	On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	overtesting, test generation, Design-for-testability, synchronous sequential circuits, redundant faults, full-scan, fault dominance
3	Irith Pomeranz, Sudhakar M. Reddy	Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	built-in test generation, synchronous sequential circuits, at-speed testing
3	Hiroyuki Higuchi	An implication-based method to detect multi-cycle paths in large sequential circuits.	DAC	2002	DBLP DOI BibTeX RDF	multi-cycle path, sequential circuits, ATPG, implication
3	Hideo Fujiwara	A New Class of Sequential Circuits with Combinational Test Generation Complexity.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
3	Irith Pomeranz, Sudhakar M. Reddy	Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	synchronous sequential circuits, test application time, Static test compaction
3	Jaan Raik, Raimund Ubar	Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	hierarchical test pattern generation, sequential circuits, register-transfer level, decision diagrams
3	Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy	SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.	VTS	2000	DBLP DOI BibTeX RDF	Test Segment, Parallel Pattern Simulator, Vector Restoration, Single Fault Restoration, Fault Coverage, Synchronous Sequential Circuits, Test Length, Static Test Compaction
3	Hideo Fujiwara	A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity.	VLSI Design	2000	DBLP DOI BibTeX RDF	complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
3	Irith Pomeranz, Sudhakar M. Reddy	On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits.	VLSI Design	2000	DBLP DOI BibTeX RDF	fault diagnosis, synchronous sequential circuits, synchronizing sequences
3	Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal	Compaction-based test generation using state and fault information.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation
3	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
3	Shiyi Xu, Wei Cen	Forecasting the efficiency of test generation algorithms for digital circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
3	Irith Pomeranz, Sudhakar M. Reddy	Fault diagnosis based on parameters of output responses.	PRDC	2000	DBLP DOI BibTeX RDF	output responses parameters, unmodeled faults, fault diagnosis, fault diagnosis, logic testing, sequential circuits, dictionaries, synchronous sequential circuits, diagnostic resolution
3	Irith Pomeranz, Sudhakar M. Reddy	On Test Compaction Objectives for Combinational and Sequential Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	combinational circuits synchronous sequential circuits test compaction tester storage schemes tester memory requirements
3	Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel	Diagnostic Simulation of Sequential Circuits Using Fault Sampling.	VLSI Design	1998	DBLP DOI BibTeX RDF	Diagnostic fault simulation, Sampling, Diagnosis, Sequential circuits
3	Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy	MIX: A Test Generation System for Synchronous Sequential Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	deterministic test generation genetic optimization based test generation restricted multiple observation time approach state based test generation synchronous sequential circuits
3	Irith Pomeranz, Sudhakar M. Reddy	Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines.	DATE	1998	DBLP DOI BibTeX RDF	synchronization, design-for-testability, synchronous sequential circuits
3	Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy	Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration.	DATE	1998	DBLP DOI BibTeX RDF	static test compaction synchronous sequential circuits
3	Peter A. Krauss, Andreas Ganz, Kurt Antreich	Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	fault parallelism, search space parallelism, sequential circuits, ATPG
3	Koji Yamazaki, Teruhiko Yamada	An approach to diagnose logical faults in partially observable sequential circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	logical faults, partially observable sequential circuits, internal nets, error sources, error propagation traceback, failing primary outputs, ISCAS'89 benchmark circuits, fault diagnosis, simulation results, probing, diagnostic resolution
3	Irith Pomeranz, Sudhakar M. Reddy	EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage.	VTS	1997	DBLP DOI BibTeX RDF	EXTEST, test generation procedure, logic testing, fault coverage, synchronous sequential circuits, test sequences
3	Irith Pomeranz, Sudhakar M. Reddy	Built-in test generation for synchronous sequential circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	comparison units, built-in self-test, synchronous sequential circuits, at-speed test
3	Martin Keim, Bernd Becker, Birgitta Stenner	On the (non-)resetability of synchronous sequential circuits.	VTS	1996	DBLP DOI BibTeX RDF	nonresetability, OBDD algorithm, three-valued based greedy algorithm, design, sequential circuits, synchronisation, heuristic algorithm, synchronous sequential circuit, synchronizing sequence, memory elements, resetability
3	Fidel Muradali, Janusz Rajski	A self-driven test structure for pseudorandom testing of non-scan sequential circuits.	VTS	1996	DBLP DOI BibTeX RDF	self-driven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuck-at fault coverage, ISCAS-89 benchmarks, logic testing, built-in self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test
3	Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs	Dynamic diagnosis of sequential circuits based on stuck-at faults.	VTS	1996	DBLP DOI BibTeX RDF	dynamic diagnosis, stuck-at fault simulation, cause-effect analysis, effect-cause analysis, error propagation back-trace, fault diagnosis, logic testing, sequential circuits, synchronous sequential circuit, matching algorithm
3	Debesh Kumar Das, Bhargab B. Bhattacharya	Does retiming affect redundancy in sequential circuits?	VLSI Design	1996	DBLP DOI BibTeX RDF	combinational redundancy, sequential redundancy, fault diagnosis, logic testing, timing, redundancy, test generation, design for testability, sequential circuits, sequential circuit, fault, retiming, logic optimization, operation speed
3	Mohamed Soufi, Yvon Savaria, F. Darlay, Bozena Kaminska	Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	full reset, initialization of sequential circuits, modelization of sequential circuits, Markov chain processes, Built-in self-testing, pseudorandom testing, testability measures, partial reset
3	Sujit Dey, Srimat T. Chakradhar	Design of testable sequential circuits by repositioning flip-flops.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	cycle-breaking, flip-flop minimization, sequential redundancy, design for testability, sequential circuits, retiming, partial scan, strongly connected components, redundant fault
3	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Resynthesis for sequential circuits designed with a specified initial state.	VTS	1995	DBLP DOI BibTeX RDF	specified initial state, retiming method, redundancy removal method, resynthesized circuit, input sequences, logic optimisation, timing, redundancy, sequential circuits, logic CAD, flip-flops, flip-flops, circuit optimisation, synchronous sequential circuits
3	Dimitrios Karayiannis, Spyros Tragoudas	Uniform area timing-driven circuit implementation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
3	Steven Parkes, Prithviraj Banerjee, Janak H. Patel	A parallel algorithm for fault simulation based on PROOFS . (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning
3	Tapan J. Chakraborty, Vishwani D. Agrawal	Robust testing for stuck-at faults.	VLSI Design	1995	DBLP DOI BibTeX RDF	logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models
3	Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Functional clock schedule optimization.	VLSI Design	1995	DBLP DOI BibTeX RDF	clock schedule optimization, time frames, level-sensitive sequential circuits, scheduling, delays, delays, timing, sequential circuits, flip-flops, clocks, circuit optimisation, latches, false paths
3	Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus	Improving topological ATPG with symbolic techniques.	VTS	1995	DBLP DOI BibTeX RDF	topological ATPG, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, network topology, automatic testing, fault coverage, binary decision diagrams, CPU time, critical areas, symbolic techniques
3	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva	A portable ATPG tool for parallel and distributed systems.	VTS	1995	DBLP DOI BibTeX RDF	portable ATPG tool, memory critical problems, electronic CAD, code portability, PVM library, DEC Alpha AXP, genetic algorithms, genetic algorithm, distributed systems, parallel architectures, parallel architectures, logic testing, message passing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, logic CAD, parallel systems, software portability, message-passing libraries, CM-5
3	Frank F. Hsu, Janak H. Patel	A distance reduction approach to design for testability.	VTS	1995	DBLP DOI BibTeX RDF	distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques
3	Mohamed Soufi, Yvon Savaria, Bozena Kaminska	On the design of at-speed testable VLSI circuits.	VTS	1995	DBLP DOI BibTeX RDF	at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
3	Bapiraju Vinnakota, Nicholas J. Stessman	Reducing test application time in scan design schemes.	VTS	1995	DBLP DOI BibTeX RDF	scan design schemes, computationally intractable problem, test vector correlation, graph theory, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic testing, fault simulation, fault coverage, correlation methods, boundary scan testing, test times, test application time, heuristic techniques
3	Irith Pomeranz, Sudhakar M. Reddy	Classification of Faults in Synchronous Sequential Circuits.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	undetectable faults, initial conditions, partially detectable faults, synchronization mode, free mode, logic testing, sequential circuits, synchronisation, fault location, synchronous sequential circuits, combinatorial circuits, test sequence, faults classification, redundant faults
3	Wu-Tung Cheng, Meng-Lin Yu	Differential fault simulation for sequential circuits.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	test generation, sequential circuits, fault simulation
2	Alexander Finder, André Sülflow, Görschwin Fey	Latency Analysis for Sequential Circuits.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Soft Error Analysis, f, Debugging, Sequential Circuits, Latency
2	Laurent Doyen, Thomas A. Henzinger, Axel Legay, Dejan Nickovic	Robustness of Sequential Circuits.	ACSD	2010	DBLP DOI BibTeX RDF	robustness, sequential circuits, continuity, Mealy machines
2	Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta	Accelerating Synchronous Sequential Circuits Using an Adaptive Clock.	VLSI Design	2010	DBLP DOI BibTeX RDF	VLSI, CAD, delays, Timing, sequential circuits, Timing optimization
2	Irith Pomeranz, Sudhakar M. Reddy	Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
2	Karthikeyan Lingasubramanian, Sanjukta Bhanja	An Error Model to Study the Behavior of Transient Errors in Sequential Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Jerzy W. Greblicki, Jerzy Kotowski	Automated Design of Totally Self-Checking Sequential Circuits.	EUROCAST	2009	DBLP DOI BibTeX RDF	sequential circuits, Fault tolerant systems, totally self-checking circuits
2	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda	An efficient fault simulation technique for transition faults in non-scan sequential circuits.	DDECS	2009	DBLP DOI BibTeX RDF
2	Natasa Miskov-Zivanov, Diana Marculescu	Modeling and Optimization for Soft-Error Reliability of Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Jun Seomun, Jae-Hyun Kim, Youngsoo Shin	Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng	An optimal algorithm for sizing sequential circuits for industrial library based designs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Wang Jian, Xu Chuanpei	Study on Test Generation of Sequential Circuits Based on Particle Swarm Optimization and Ant Algorithm.	CSSE	2008	DBLP DOI BibTeX RDF
2	Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri	A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Martin Trefzer, Tüze Kuyucu, Andrew J. Greensted, Julian Francis Miller, Andy M. Tyrrell	The Input Pattern Order Problem: Evolution of Combinatorial and Sequential Circuits in Hardware.	ICES	2008	DBLP DOI BibTeX RDF
2	Hyein Lee, Seungwhun Paik, Youngsoo Shin	Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Min-Lun Chuang, Chun-Yao Wang	Synthesis of reversible sequential elements.	JETC	2008	DBLP DOI BibTeX RDF	sequential elements, sequential circuits, Reversible logic
2	Irith Pomeranz	Invariant States and Redundant Logic in Synchronous Sequential Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Fatih Kocan, Daniel G. Saab	Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Dynamic fault diagnosis, FPGA, Emulation, Stuck-at faults, Circuits, Gate-level
2	Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus	Hierarchical Identification of Untestable Faults in Sequential Circuits.	DSD	2007	DBLP DOI BibTeX RDF
2	Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid	Sequential circuits for program analysis.	ASE	2007	DBLP DOI BibTeX RDF	model checking, verification, static analysis, program analysis
2	Jun Seomun, Jaehyun Kim, Youngsoo Shin	Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits.	DAC	2007	DBLP DOI BibTeX RDF
2	Natasa Miskov-Zivanov, Diana Marculescu	Soft error rate analysis for sequential circuits.	DATE	2007	DBLP DOI BibTeX RDF
2	Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler	SAT-based ATPG for Path Delay Faults in Sequential Circuits.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid	Sequential Circuits for Relational Analysis.	ICSE	2007	DBLP DOI BibTeX RDF
2	Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait	Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Jerzy W. Greblicki	CAD software for designing of Totally Self Checking Sequential Circuits.	DepCoS-RELCOMEX	2006	DBLP DOI BibTeX RDF
2	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu	Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen	Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja	Combinational automatic test pattern generation for acyclic sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu	A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Irith Pomeranz, Sudhakar M. Reddy	On masking of redundant faults in synchronous sequential circuits with design-for-testability logic.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Anand L. D'Souza, Michael S. Hsiao	Error Diagnosis of Sequential Circuits Using Region-Based Model.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	non-enumerative, diagnosis, sequential, region-based
2	Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait	Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
2	Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar	Improved Fault Emulation for Synchronous Sequential Circuits.	DSD	2005	DBLP DOI BibTeX RDF