Search results for "signal delay"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	V. Chandramouli, Karem A. Sakallah, Ayman I. Kayssi	Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity.	ARVLSI	1997	DBLP DOI BibTeX RDF	Coupled interconnects, Distributed lines, Proximity effects, Interconnect delay, Moment matching
2	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
2	Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo	Interconnect design for deep submicron ICs.	ICCAD	1997	DBLP DOI BibTeX RDF	required-arrival-time Steiner tree higher-order moment signal delay and integrity
2	Bernhard Hoppe, Gerd Neuendorf, Doris Schmitt-Landsiedel, J. Will Specks	Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
2	Pak K. Chan, Kevin Karplus	Computing signal delay in general RC networks by tree/link partitioning.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
2	Pak K. Chan, Kevin Karplus	Computing Signal Delay in General RC Networks by Tree/Link Partitioning.	DAC	1989	DBLP DOI BibTeX RDF
1	Wu Fang, Zhang Huowen, Duan Lei, Lai Jinmei, Wang Yuan, Tong Jiarong	A delay-optimized universal FPGA routing architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Power-delay optimization in VLSI microprocessors by wire spacing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Wire spacing, power optimization, interconnect optimization, delay-optimization
1	Thomas Popp, Mario Kirschbaum, Stefan Mangard	Practical Attacks on Masked Hardware.	CT-RSA	2009	DBLP DOI BibTeX RDF	DPA-Resistant Masked Logic Styles, MDPL, Prototype Chip, Hardware AES, PDF-Attack, PRNG
1	Waqas ur Rehman, Eyal de Lara, Stefan Saroiu	CILoS: a CDMA indoor localization system.	UbiComp	2008	DBLP DOI BibTeX RDF	localization system, radio fingerprinting, location
1	Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi	An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty.	DSD	2008	DBLP DOI BibTeX RDF
1	Heinrich W. Löllmann, Guido Dartmann, Peter Vary	Least-squares design of subsampled allpass transformed DFT filter-banks with LTI property.	ICASSP	2008	DBLP DOI BibTeX RDF
1	Heinrich W. Löllmann, Peter Vary	Design of IIR QMF banks with near-perfect reconstruction and low complexity.	ICASSP	2008	DBLP DOI BibTeX RDF
1	Kai Steinert, Martin Schönle, Christophe Beaugeant, Tim Fingscheidt	Hands-free system with low-delay subband acoustic echo control and noise reduction.	ICASSP	2008	DBLP DOI BibTeX RDF
1	Jingye Xu, Pervez Khaled, Masud H. Chowdhury	Full waveform accuracy to estimate delay in coupled digital circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Rohit Singhal, Gwan Choi, Rabi N. Mahapatra	Data Handling Limits of On-Chip Interconnects.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	David Meisner, Sherief Reda	Hardware libraries: An architecture for economic acceleration in soft multi-core environments.	ICCD	2007	DBLP DOI BibTeX RDF
1	Yaoting Jiao, Yulu Yang, Ming He, Mei Yang, Yingtao Jiang	Multi-path Routing for Mesh/Torus-Based NoCs.	ITNG	2007	DBLP DOI BibTeX RDF
1	Basab Datta, Wayne P. Burleson	Low power on-chip thermal sensors based on wires.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani	How does partitioning matter for 3D floorplanning?	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	partitioning, floorplanning, 3D IC, wire length
1	Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner	A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra	Information theoretic approach to address delay and reliability in long on-chip interconnects.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Michael Kropfitsch, Philipp Riess, Gerhard Knoblinger, Dieter Draxelmayr	Dielectric absorption of low-k materials: extraction, modelling and influence on SAR ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
1	K. Mustafa, Ian C. Bruce	Robust formant tracking for continuous speech with speaker variability.	IEEE Transactions on Audio, Speech & Language Processing	2006	DBLP DOI BibTeX RDF
1	Wenjian Yu, Mengsheng Zhang, Zeyi Wang	Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Syed Suhaib, Deepak Mathaikutty, David Berner, Sandeep K. Shukla	Validating Families of Latency Insensitive Protocols.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	long interconnects, latency insensitive protocols, splitter, verification framework, Simulation, formal verification, merger, relay station
1	Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier	Modeling of Crosstalk Fault in Defective Interconnects.	PATMOS	2006	DBLP DOI BibTeX RDF	defect-based-crosstalk fault model, signal integrity losses, aggres-sor-victim, ABCD-model, crosstalk-hazards
1	Medha Kulkarni, Tom Chen	A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Heinrich W. Löllmann, Peter Vary	Generalized filter-bank equalizer for noise reduction with reduced signal delay.	INTERSPEECH	2005	DBLP BibTeX RDF
1	Amitava Bhaduri, Ranga Vemuri	Moment-driven coupling-aware routing methodology.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	coupling-aware, routing, moments
1	Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner	A linear model for high-level delay estimation in VDSM on-chip interconnects.	ISCAS	2005	DBLP DOI BibTeX RDF
1	T. Chen	On the impact of on-chip inductance on signal nets under the influence of power grid noise.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Medha Kulkarni, Tom Chen	A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects.	ISQED	2004	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Igor L. Markov, Sherief Reda	Boosting: Min-Cut Placement with Improved Signal Delay.	DATE	2004	DBLP DOI BibTeX RDF
1	Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis	Accurate capture of timing parameters in inductively-coupled on-chip interconnects.	SBCCI	2004	DBLP DOI BibTeX RDF	signal delay, crosstalk, on-chip interconnects, interconnect models, inductive coupling
1	Xiaoping Tang, Martin D. F. Wong	Tradeoff routing resource, runtime and quality in buffered routing.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Martin Danek, Josef Kolar	FPGA modelling for high-performance algorithms.	FPGA	2004	DBLP DOI BibTeX RDF
1	Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris	Fast adders in modern FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
1	Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen	A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Lei Wang, Sandeep K. Gupta, Melvin A. Breuer	Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Hemant Mahawar, Vivek Sarin	Parallel Software for Inductance Extraction.	ICPP	2004	DBLP DOI BibTeX RDF	Inductance extraction, Mixed mode parallelization, Parallel computing, Iterative methods, Preconditioning
1	Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim	A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Hemant Mahawar, Vivek Sarin, Ananth Grama	Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction.	HiPC	2004	DBLP DOI BibTeX RDF
1	Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel	Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner	On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Yu Chen, Puneet Gupta, Andrew B. Kahng	Performance-impact limited area fill synthesis.	DAC	2003	DBLP DOI BibTeX RDF	VLSI manufacturability, coupling capacitance extraction, dummy fill problem, signal delay, linear programming, greedy method
1	Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden	Benchmarking for large-scale placement and beyond.	ISPD	2003	DBLP DOI BibTeX RDF	placer, signal delay, performance, evaluation, routing, benchmark, timing, placement, layout, congestion, comparison, wirelength
1	Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi	CMOS flash analog-to-digital converter for high speed and low voltage applications.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	TIQ comparator, fat tree encoder, flash ADC, analog-to-digital converter, low voltage, high speed
1	Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman	Reduced Delay Uncertainty in High Performance Clock Distribution Networks.	DATE	2003	DBLP DOI BibTeX RDF
1	Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester	Optimal Inductance for On-chip RLC Interconnections.	ICCD	2003	DBLP DOI BibTeX RDF
1	Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Christophe Bobda	A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
1	Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao	Maze routing with buffer insertion under transition time constraints.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	H. Bernhard Pogge	The next chip challenge: effective methods for viable mixed technology SoCs.	DAC	2002	DBLP DOI BibTeX RDF	SoCs (System on a Chip), chip fabrication methods, chip subsector concepts, chip/packing integration
1	Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou	Track assignment: a desirable intermediate step between global routing and detailed routing.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw	Estimation of signal arrival times in the presence of delay noise.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim	Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects.	SLIP	2002	DBLP DOI BibTeX RDF	TWA, signal integrity verification, delay, crosstalk, ringing, signal integrity, transmission line, glitch, VLSI interconnect, traveling-wave
1	Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie	Wire layer geometry optimization using stochastic wire sampling.	SLIP	2002	DBLP DOI BibTeX RDF	genetic algorithms, optimization, interconnect, Rent's rule
1	Shane Dougherty, Raymond R. Hill, James T. Moore	Unmanned aerial vehicles: modeling signal latency effects using arena?	Winter Simulation Conference	2002	DBLP DOI BibTeX RDF
1	Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao	Maze Routing with Buffer Insertion under Transition Time Constraints.	DATE	2002	DBLP DOI BibTeX RDF
1	Hemant Mahawar, Vivek Sarin, Weiping Shi	Fast Inductance Extraction of Large VLSI Circuits. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	Inductance extraction, VLSI, parallel computing, iterative methods, preconditioning
1	Igor D. D. Curcio, Miikka Lundan	SIP call setup delay in 3G networks.	ISCC	2002	DBLP DOI BibTeX RDF
1	Yongjian Brandon Guo, K. Wayne Current	Voltage Comparator Circuits for Multiple-Valued CMOS Logic. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF	voltage comparator, MVL, low-power, CMOS
1	Yungseon Eo, Jongin Shim, William R. Eisenstadt	A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim	Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman	Retiming and clock scheduling for digital circuit optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq Bustami, Don MacMillen, Jacob K. White	Managing on-chip inductive effects.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Andreas Schierwagen, Conny Claus	Dendritic morphology and signal delay in superior colliculus neurons.	Neurocomputing	2001	DBLP DOI BibTeX RDF
1	Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou	A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Angelo Brambilla, Paolo Maffezzoni	Statistical method for the analysis of interconnects delay insubmicrometer layouts.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Jason Cong, Cheng-Kok Koh, Patrick H. Madden	Interconnect layout optimization under higher order RLC model forMCM designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw	On-chip inductance modeling and analysis.	DAC	2000	DBLP DOI BibTeX RDF
1	David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang	On-chip inductance modeling.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
1	Kevin T. Tang, Eby G. Friedman	Noise estimation due to signal activity for capacitively coupled CMOS logic gates.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
1	Erik A. McShane, Krishna Shenai	Correct-by-Design CAD Enhancement for EMI Signal Integrity.	ISQED	2000	DBLP DOI BibTeX RDF
1	Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El Gamal	Optimizing dominant time constant in RC circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Ut-Va Koc, K. J. Ray Liu	DCT-based motion estimation.	IEEE Transactions on Image Processing	1998	DBLP DOI BibTeX RDF
1	Lieven Vandenberghe, Stephen P. Boyd, Abbas El Gamal	Optimal wire and transistor sizing for circuits with non-tree topology.	ICCAD	1997	DBLP DOI BibTeX RDF	optimal circuit sizing, crosstalk, Elmore delay, clock distribution networks
1	Masato Edahiro, Richard J. Lipton	Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	VLSI, CAD, Placement, Layout, Buffer, Clock
1	Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng	Performance driven bus buffer insertion.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
1	Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger	Prim-Dijkstra tradeoffs for improved performance-driven routing tree design.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins	Near-optimal critical sink routing tree constructions.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Chunduri Rama Mohan, Partha Pratim Chakrabarti	A new approach for factorizing FSM's.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Neven Orhanovic, Paul Wang, Vijay K. Tripathi	Time-domain simulation of uniform and nonuniform multiconductor lossy lines by the method of characteristics.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Jiri Vlach, James A. Barby, Anthony Vannelli, T. Talkhan, C.-J. Richard Shi	Group delay as an estimate of delay in logic.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
1	Veronika Eisele, Bernhard Hoppe, Oliver Kiehl	Transmission gate delay models for circuit optimization.	EURO-DAC	1990	DBLP DOI BibTeX RDF
1	Pak K. Chan, Martine D. F. Schlag	Bounds on signal delay in RC mesh networks.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
1	Yasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba	Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs.	DAC	1986	DBLP DOI BibTeX RDF
1	Tzu-Mu Lin, Carver Mead	Signal Delay in General RC Networks.	IEEE Trans. on CAD of Integrated Circuits and Systems	1984	DBLP DOI BibTeX RDF
1	Jorge Rubinstein, Paul Penfield Jr., Mark A. Horowitz	Signal Delay in RC Tree Networks.	IEEE Trans. on CAD of Integrated Circuits and Systems	1983	DBLP DOI BibTeX RDF
1	Paul Penfield Jr., Jorge Rubinstein	Signal delay in RC tree networks.	DAC	1981	DBLP BibTeX RDF