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Results
Found 3 publication records. Showing 3 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Wen-Jer Wu, Chuan Yi Tang |
Memory test time reduction by interconnecting test items.  |
Asian Test Symposium  |
2000 |
DBLP DOI BibTeX RDF |
memory test time reduction, test items interconnection, initialization sequences, verification sequences, signal settling time, interconnection problem, rural Chinese postman problem, integer linear programming model, successive ILP models, graph theory, constraints, linear programming, integrated circuit testing, integer programming, iterations, NP-hard problem, integrated memory circuits |
| 2 | Jason Cong, Cheng-Kok Koh |
Interconnect layout optimization under higher-order RLC model.  |
ICCAD  |
1997 |
DBLP DOI BibTeX RDF |
RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization |
| 1 | Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo |
Interconnect design for deep submicron ICs.  |
ICCAD  |
1997 |
DBLP DOI BibTeX RDF |
required-arrival-time Steiner tree higher-order moment signal delay and integrity |
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