Search results for "simultaneous multi-threading (smt)"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	James Burns, Jean-Luc Gaudiot	Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight?	HPCA	2000	DBLP DOI BibTeX RDF	Simultaneous Multi-Threading (SMT)
1	Stijn Eyerman, Lieven Eeckhout	Probabilistic job symbiosis modeling for SMT processor scheduling.	ASPLOS	2010	DBLP DOI BibTeX RDF	simultaneous multi-threading (smt), symbiotic job scheduling, performance modeling
1	Subhash Saini, Andrey Naraikin, Rupak Biswas, David Barkai, Timothy Sandstrom	Early performance evaluation of a "Nehalem" cluster using scientific and engineering applications.	SC	2009	DBLP DOI BibTeX RDF
1	Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi	PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Zeshan Chishti, T. N. Vijaykumar	Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Power Management, Performance of Systems, Multithreaded processors
1	Peter Rounce, Alberto Ferreira de Souza	Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	Simultaneous multi-threading, Wide issue architectures, VLIW, Dynamic instruction scheduling
1	Linzhi Ning, Wenbin Yao, Jun Ni, Nianmin Yao	Fault-Tolerance CMP Architecture based on SMT Technology.	IMSCCS	2007	DBLP DOI BibTeX RDF	fault tolerance, CMP, thread, SMT
1	Xing Fang, Dong Wang, Shuming Chen	Exploiting Thread-Level Parallelism of Irregular LDPC Decoder with Simultaneous Multi-threading Technique.	APPT	2007	DBLP DOI BibTeX RDF
1	Håkan Zeffer, Zoran Radovic, Martin Karlsson, Erik Hagersten	TMA: a trap-based memory architecture.	ICS	2006	DBLP DOI BibTeX RDF	distributed shared memory (DSM), low complexity server design, node coherence checks, server design, simultaneous multi-threading (SMT), software coherence, trap-based memory architecture (TMA), chip multi processor (CMP)
1	Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha	HybDTM: a coordinated hardware-software approach for dynamic thermal management.	DAC	2006	DBLP DOI BibTeX RDF	hybrid hardware-software management, thermal model, dynamic thermal management
1	Joseph J. Sharkey, Dmitry Ponomarev	Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch.	ICPP	2006	DBLP DOI BibTeX RDF
1	Xiaobin Li, Jean-Luc Gaudiot	Design Trade-Offs and Deadlock Prevention in Transient Fault-Tolerant SMT Processors.	PRDC	2006	DBLP DOI BibTeX RDF
1	Daniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor, Diederik Verkest	Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham	Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor.	MICRO	2005	DBLP DOI BibTeX RDF
1	James Burns, Jean-Luc Gaudiot	Area and System Clock Effects on SMT/CMP Throughput.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	layout area estimation, microarchitecture trade off, processor architecture, SMT
1	Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson	Design and implementation of the POWER5 microprocessor.	DAC	2004	DBLP DOI BibTeX RDF	POWER5, simultaneous multi-threading (SMT), clock gating, power reduction, microprocessor design, temperature sensor
1	Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen	Conjoined-Core Chip Multiprocessing.	MICRO	2004	DBLP DOI BibTeX RDF
1	Tomasz Madajczak	An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures.	PARELEC	2004	DBLP DOI BibTeX RDF
1	Ali El-Moursy, David H. Albonesi	Front-End Policies for Improved Issue Efficiency in SMT Processors.	HPCA	2003	DBLP DOI BibTeX RDF
1	James Burns, Jean-Luc Gaudiot	SMT Layout Overhead and Scalability.	IEEE Trans. Parallel Distrib. Syst.	2002	DBLP DOI BibTeX RDF	layout area estimation, microarchitecture trade-off, processor architecture, SMT
1	James Burns, Jean-Luc Gaudiot	Area and System Clock Effects on SMT/CMP Processors.	IEEE PACT	2001	DBLP DOI BibTeX RDF
1	Steven Wallace, Brad Calder, Dean M. Tullsen	Threaded Multiple Path Execution.	ISCA	1998	DBLP DOI BibTeX RDF